Abstract: In order to avoid hardware pipeline breaks and also to enhance performance when emulating a target system in a host system employing a central processing unit including a plurality of execution units, three major pieces of processing that are required for handling every emulated instruction are overlapped. This overlap includes: 1) the instruction fetch of the emulated instruction by the emulation software, 2) the branching of the emulation code based upon the opcode of the emulated instruction to be executed and 3) the actual execution processing for each emulated instruction. The branching of the emulation code, depending upon the opcode of each instruction, utilizes special instructions configured to minimize pipeline breaks on the host system hardware and thus to minimize the effective minimum host system processing time for the simplest emulated instructions.

Abstract: An integrated circuit structure and a method of manufacturing, wherein the method comprises forming a first via in an interconnect layer of the substrate, wherein the first via comprises a first size diameter; and forming a second via in the interconnect layer, wherein the second via comprises a second size diameter, the second size diameter being dimensioned larger than the first size diameter, wherein the second via comprises a non-uniform circumference, and wherein the substrate is configured in an approximately 1:1 ratio (i.e., approximately equal number) of the first and second vias. The first and second vias are laser formed or are formed by any of mechanical punching and photolithography. The second via is formed by sequentially forming multiple partially overlapping vias dimensioned and configured with the first size diameter. The first and second vias are arranged in a grid to allow for wiring of electronic devices.

Abstract: A methodology for improving the timing of specific critical paths in a Field Programmable Gate Array (FPGA) implementation of a logic circuit without significantly affecting the timing of other logic paths. The method utilizes logic replication and specific guidelines for placement of the logic gates involved in a critical path to optimize the timing of that critical path. The logic gates involved in a critical path are either replicated and placed, or simply moved, in order to implement the desired logic with nearly the shortest total distance for routing of signals involved in the critical path. The optimization is carried out with relatively little impact on the timing of other paths and is applicable to FPGAs in which the signal delay between any source and gate is relatively independent of the fanout of the source signal to any other loads.

Abstract: In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by utilizing a plurality of sets of registers maintained in a round-robin system. Whenever a transition is made to a higher security environment, a switch is made to a different set of registers. Then, when a transition is made back to the lower security environment, a switch is made back to the previous set of registers. Writes to memory copies of registers are detected, and only those registers whose memory copies have been modified are restored from the memory copy.