Abstract: An 8-to-256 address signal decoder is composed of sixteen 4-to-16 output decoders. Each 4-to-16 decoder is subdivided into eight sub-functions having outputs ANDed together using sixteen OR gates. Each 4-input NAND gate of a conventional rectangular decoder is replaced by two input sub-function NANDs feeding an OR gate. The two sub-function NANDs are positioned outside a high density region, whereas the OR gates reside within a high density region below a memory cell array. The sixteen OR gates are distributed in a 4.times.4 array format. Each OR gate column is four basic cells wide, and there are four output lines for each column of OR gates to conform to dense memory cell layout criteria. The array structure requires only one vertical input line per column and one horizontal input line per row to reach each OR gate. Inverting drivers required to complete the 4-to-16 output decoders are arranged in a 4.times.4 array. The position of each inverter corresponds to the OR gate that drives it.