Abstract: A media stream receiver is provided for scalable physical layer flow of packetized media streams. The media stream receiver replicates the processing block in time, rather than in hardware, through the use of a single shared memory and pointer alignment calculations, which combines multiple buffering stages as the single, shared memory buffer to offer redundancy and alignment, while acting as a receiver buffer to account for packet delay variations. By doing so the media stream receiver can perform a vertical interval switch between received media streams.

Abstract: A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device.

Abstract: A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device.

Abstract: A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device.

Abstract: A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device.

Abstract: An IP router capable of isochronous switching of a packetized media stream. According to an example, the IP router parses the RTP header within an incoming IP datagram to extract the RTP time stamp, which provides a time value for a unique IP Flow. By inspecting the header, the IP router can switch the flow at the point in time that the RTP time stamp value changes, or matches a target value. In one aspect, the IP router looks for the change in the RTP time stamp value and performs the switch based on the detected change. In another aspect, the IP router performs the switch at a specified time stamp value that can be unique to a group of signals or based on a common “sync” value published to all the ports of the IP router.

Abstract: An IP router capable of isochronous switching of a packetized media stream. According to an example, the IP router parses the RTP header within an incoming IP datagram to extract the RTP time stamp, which provides a time value for a unique IP Flow. By inspecting the header, the IP router can switch the flow at the point in time that the RTP time stamp value changes, or matches a target value. In one aspect, the IP router looks for the change in the RTP time stamp value and performs the switch based on the detected change. In another aspect, the IP router performs the switch at a specified time stamp value that can be unique to a group of signals or based on a common “sync” value published to all the ports of the IP router.

Abstract: A system and method is provided for minimizing delay time for controlling media content capture during live video broadcast production. The system includes a video production receiver that receives media content streams from one or more cameras that includes live media content captured by the cameras and encoded in a first encoding format. Moreover, a multi-view interface displays the media content and a video production controller generates control instructions based on inputs to the interface to change operation of the cameras capturing the respective media content. A camera controller is included that transmits the generated control instructions to the cameras to change the operation for capturing the respective media content. Moreover, the video production controls production of a live video stream for video broadcast production using media content that is captured from the cameras and that is encoded in a second encoding format different than the first encoding format.

Abstract: A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device.

Abstract: An IP router capable of isochronous switching of a packetized media stream. According to an example, the IP router parses the RTP header within an incoming IP datagram to extract the RTP time stamp, which provides a time value for a unique IP Flow. By inspecting the header, the IP router can switch the flow at the point in time that the RTP time stamp value changes, or matches a target value. In one aspect, the IP router looks for the change in the RTP time stamp value and performs the switch based on the detected change. In another aspect, the IP router performs the switch at a specified time stamp value that can be unique to a group of signals or based on a common “sync” value published to all the ports of the IP router.

Abstract: A media stream receiver is provided for scalable physical layer flow of packetized media streams. The media stream receiver replicates the processing block in time, rather than in hardware, through the use of a single shared memory and pointer alignment calculations, which combines multiple buffering stages as the single, shared memory buffer to offer redundancy and alignment, while acting as a receiver buffer to account for packet delay variations. By doing so the media stream receiver can perform a vertical interval switch between received media streams.

Abstract: A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device.

Abstract: The present aspects relate to techniques of timing synchronization of audio and video (AV) data in a network. In particular, the techniques for a AV master to distribute AV data encoded with one or more time markers to a plurality of processing nodes. The one or more time markers may be indexed to a precision time protocol (PTP) time stamp used as a time reference. In one technique, the nodes extract the time markers to determine an offset value that is applied to a PLL to synchronize AV data packets at a distribution node or a processing node. In another technique the distribution node or the processing node determines the worst case path, which corresponds to a system offset value. The distribution node then reports the system offset value to the AV master, which in turn adjusts the phase based on the report.

Abstract: The present aspects relate to techniques of timing synchronization of audio and video (AV) data in a network. In particular, the techniques for a AV master to distribute AV data encoded with one or more time markers to a plurality of processing nodes. The one or more time markers may be indexed to a precision time protocol (PTP) time stamp used as a time reference. In one technique, the nodes extract the time markers to determine an offset value that is applied to a PLL to synchronize AV data packets at a distribution node or a processing node. In another technique the distribution node or the processing node determines the worst case path, which corresponds to a system offset value. The distribution node then reports the system offset value to the AV master, which in turn adjusts the phase based on the report.

Abstract: The present aspects relate to techniques of timing synchronization of audio and video (AV) data in a network. In particular, the techniques for a AV master to distribute AV data encoded with one or more time markers to a plurality of processing nodes. The one or more time markers may be indexed to a precision time protocol (PTP) time stamp used as a time reference. In one technique, the nodes extract the time markers to determine an offset value that is applied to a PLL to synchronize AV data packets at a distribution node or a processing node. In another technique the distribution node or the processing node determines the worst case path, which corresponds to a system offset value. The distribution node then reports the system offset value to the AV master, which in turn adjusts the phase based on the report.

Abstract: A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device.

Abstract: A method, a system, an apparatus, and a computer program product for multi-protocol end-to-end control in a hybrid broadcast production environment. A topology model of a hybrid broadcast production system is stored, the topology model comprising connections between pieces of equipment and characteristics of each piece of equipment, the equipment including at least one broadcast router and one IP router. After receipt of information regarding a received media signal and of an intended destination for the media signal, a traffic flow for the media signal is determined based on the stored topology model of the system. Then, the broadcast router and IP router are controlled to enable the determined traffic flow.

Abstract: A router has multiple channel inputs and multiple channel outputs and a switch core for selectively connecting at least two of the channel outputs to respective channel inputs. Each channel output is connected to an output signal path containing a FIFO register and the router is configured so that first and second channel outputs are connected to a pair of channel inputs respectively. The router configuration is changed so that the first and second channel outputs are connected to first and second channel inputs respectively. The FIFO registers in the output signal paths of the first and second channel outputs are forced to equal fullness.

Abstract: A composite input signal having an audio component and a video component is routed from an input to an output by separating a stream of audio data words at an average frequency F1 from the video component and supplying the separated stream of audio data words sequentially to a FIFO input register. The output of the FIFO input register is polled at a frequency F2, greater than F1, and, in the event that an audio data word is available at the output of the FIFO input register, the audio data word is conveyed from the output of the FIFO input register to an input of a signal path. Otherwise a null data word is conveyed to the input of the signal path. The signal path thereby conveys a stream of data words that comprises both audio data words and null data words. The audio data words of the stream conveyed by the path are combined with the video component of the composite input signal.

Abstract: A composite input signal having an audio component and a video component is routed from an input to an output by separating a stream of audio data words at an average frequency F1 from the video component and supplying the separated stream of audio data words sequentially to a FIFO input register. The output of the FIFO input register is polled at a frequency F2, greater than F1, and, in the event that an audio data word is available at the output of the FIFO input register, the audio data word is conveyed from the output of the FIFO input register to an input of a signal path. Otherwise a null data word is conveyed to the input of the signal path. The signal path thereby conveys a stream of data words that comprises both audio data words and null data words. The audio data words of the stream conveyed by the path are combined with the video component of the composite input signal.