Abstract: A process for passivating, and optionally stripping and inhibiting corrosion of an etched substrate (20), is described. In the process, a substrate (20) having etchant byproducts (24) thereon, is placed into a vacuum chamber (52), and passivated in a multicycle passivation process comprising at least two passivating steps. In each passivating step, passivating gas is introduced into the vacuum chamber (52) and a plasma is generated from the passivating gas. When the substrate also has remnant resist (26) thereon, the resist (26) is stripped in a multicycle passivation and stripping process, each cycle including a passivating step and a stripping step. The stripping step is performed by introducing a stripping gas into the vacuum chamber (52) and generating a plasma from the stripping gas. In the multicycle process, the passivating and optional stripping steps, are repeated at least once in the same order that the steps were done.

Abstract: A plasma processing apparatus including a wafer supporting pedestal which is designed to reduce particle trapping phenomena. In a region of the pedestal surface which surrounds or abuts the wafer, the pedestal has a permittivity which is substantially equal to or greater than that of the wafer surface. As a result, the sheath boundary is reshaped to reduce particle trapping.

Abstract: The plasma dry cleaning rate of semiconductor process chamber walls can be improved by placing a non-gaseous dry cleaning enhancement material in the position which was occupied by the workpiece during semiconductor processing. The non-gaseous dry cleaning enhancement material is either capable of generating dry cleaning reactive species and/or of reducing the consumption of the dry cleaning reactive species generated from the plasma gas feed to the process chamber.When process chamber non-volatile contaminant deposits are removed from plasma process chamber surfaces during plasma dry cleaning by placing a non-gaseous source of reactive-species-generating material within the plasma process chamber, the non-gaseous source of reactive-species-generating material need not be located upon or adjacent the workpiece support platform: however, this location provides excellent cleaning results in typical process chamber designs.

Abstract: A technique for removing particles from above a semiconductor wafer, particularly particles that are trapped in a plasma chamber during processing of the wafer. Trapped particles are usually not all drawn out with gases exhausted from the chamber, in part because a peripheral focus ring and clamping mechanism impede their flow. In the method of the invention, the focus ring and clamping mechanism are raised on completion of processing, but before radio-frequency (rf) power is disconnected from the process chamber. Trapped particles are then easily flowed from the chamber with an introduced inert gas, and the level of particulate contamination of the wafer is significantly reduced.

Abstract: A process for etching aluminum from a substrate, where portions of the aluminum are protected by a resist material, is described. The substrate is placed into a chamber and a process gas comprising HCl, Cl-containing etchant and N.sub.2 is introduced in the chamber. A plasma is generated in the chamber to generate from the process gas an etch gas that etches aluminum from the substrate at fast rates, with good selectivity, reduced profile microloading, and substantially only anisotropic etching.

Abstract: A process for selectively etching a substrate, having grain boundaries and a resist material thereon, is described. The substrate is placed into an etch zone and a process gas comprising a primary etchant, a secondary etchant, and xenon is introduced into the etch zone. A plasma is generated in the zone to form an etch gas from the process gas, that substantially anisotropically etches the substrate at fast rates, with good selectivity, and reduced profile microloading. Preferably the primary etchant comprises Cl.sub.2, and the secondary etchant comprises BCl.sub.3.

Abstract: A process is described for removing from an integrated circuit structure photoresist remaining after a metal etch which also removes or inactivates a sufficient amount of any remaining chlorine residues remaining from the previous metal etch to inhibit corrosion of the remaining metal for at least 24 hours. The process includes a first stripping step associated with a plasma, using either O.sub.2 gas and one or more fluorocarbon gases, or O.sub.2 gas and N.sub.2 gas; followed by a subsequent step using a combination of H.sub.2 O.sub.2 /H.sub.2 O vapors, O.sub.2 gas, and optionally N.sub.2 gas associated with a plasma. Preferably, the plasma is generated in a microwave plasma generator located upstream of the stripping chamber, and the stripping gases pass through this generator so that reactive species produced from the gases in the plasma enter the stripping chamber.

Abstract: A method of fabricating higher-order metal interconnection layers in a multi-level metal semiconductor device. The semiconductor device has at least one metal layer, an oxide layer disposed on the metal layer, and a metal plug disposed in the oxide layer connected to the metal layer. A reverse photoresist mask is formed on the oxide layer that is etched to form trenches therein that define the higher-order metal layer. An adhesion layer that comprises titanium tungsten or aluminum is deposited on top of the photoresist mask that contacts the metal plug. A low viscosity photoresist layer is then deposited on top of the adhesion layer. The adhesion layer and low viscosity photoresist layer are then anisotropically etched, and the low viscosity photoresist layer is then removed to expose the adhesion layer. Finally, selective metal, such as tungsten or molybdenum, for example, is deposited on top of the adhesion layer in the trench to form the higher-order metal interconnection layer.

Abstract: Methods of fabricating metal interconnection lines in an integrated circuit. In general, one method comprises the steps of depositing a layer of metal on an inter-dielectric oxide layer. The layer of metal is patterned and etched to form metal interconnection lines over the oxide layer. Tungsten is selectively deposited onto the etched layer to completely form the metal interconnection lines. Additionally, in a second method, a layer of tungsten may be deposited prior to the layer of metal. This forms a metal line that is completely encapsulated in tungsten. In addition, selective tungsten employed to repair broken metal lines in a fabricated integrated circuit. The selective tungsten is deposited using a chemical vapor deposition process and is deposited onto masked and etched second level (or higher) metal lines formed in the integrated circuit. The method of selectively depositing tungsten comprises the steps of exposing the metal interconnection lines to a mixture of SiH.sub.