Abstract: A circuit includes a processing circuit. The processing circuit is configured to model a battery using a battery model. The battery model includes: a voltage terminal, an RC stage having a first resistor and a first capacitor in parallel, a second resistor, a second capacitor and a ground terminal. The second resistor is coupled between the voltage terminal and the RC stage. The RC stage is coupled between the second resistor and the second capacitor. The second capacitor is coupled between the RC stage and the ground terminal. The processing circuit is also configured to determine a first resistance of the first resistor based on a first ratio of the first resistance to a total battery resistance, determine a second resistance of the second resistor based on a second ratio of the second resistance to the total battery resistance, and determine the total battery resistance.

Abstract: Using a phase interferometry method which utilizes both amplitude and phase allows the determination and estimation of multipath signals. To determine the location of an object, a signal that contains sufficient information to allow determination of both amplitude and phase, like a packet that includes a sinewave portion, is provided from a master device. A slave device measures the phase and amplitude of the received packet and returns this information to the master device. The slave device returns a packet to the master that contains a similar sinewave portion to allow the master device to determine the phase and amplitude of the received signals. Based on the two sets of amplitude and phase of the RF signals, the master device utilizes a fast Fourier transform or techniques like multiple signal classification to determine the indicated distance for each path and thus more accurately determines a location of the slave device.

Abstract: Using a phase interferometry method which utilizes both amplitude and phase allows the determination and estimation of multipath signals. To determine the location of an object, a signal that contains sufficient information to allow determination of both amplitude and phase, like a packet that includes a sinewave portion, is provided from a master device. A slave device measures the phase and amplitude of the received packet and returns this information to the master device. The slave device returns a packet to the master that contains a similar sinewave portion to allow the master device to determine the phase and amplitude of the received signals. Based on the two sets of amplitude and phase of the RF signals, the master device utilizes a fast Fourier transform or techniques like multiple signal classification to determine the indicated distance for each path and thus more accurately determines a location of the slave device.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: A process of estimating an admittance of an RF component using a ladder network with alternating series and parallel components by making three VSWR measurements and computing three admittance circle solutions in the complex admittance plane. The admittances circles are transformed through reference planes of the ladder network to obtain three RF component admittance circles, then estimating the RF component admittance using three nearest intersections of the three RF component admittance circles. Reference planes are defined immediately upstream and immediately downstream of each component of the ladder network. The transforms are performed using lumped parameter models of the series and parallel components of the ladder network.

Abstract: An analog-to-digital converter (ADC) is provided. The ADC includes a plurality of pipelined ADCs and an adjustment circuit. Each pipelined ADC is adapted to receive an analog input signal, has an adjustable transfer function, and includes a compensator. The adjustment circuit is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error.

Abstract: Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.

Abstract: A process of estimating an admittance of an RF component using a ladder network with alternating series and parallel components by making three VSWR measurements and computing three admittance circle solutions in the complex admittance plane. The admittances circles are transformed through reference planes of the ladder network to obtain three RF component admittance circles, then estimating the RF component admittance using three nearest intersections of the three RF component admittance circles. Reference planes are defined immediately upstream and immediately downstream of each component of the ladder network. The transforms are performed using lumped parameter models of the series and parallel components of the ladder network.

Abstract: A method and apparatus for estimating Doppler channel in an Orthogonal Frequency-Division Multiplexor. The method includes selecting a continuation pilot, generating a channel estimation, filtering the continual pilot with at least one channel estimator, computing the error between the channel estimation and the filtered channel estimates, averaging the error across continual pilot carriers and over time, estimating noise variance, corrects average error utilizing the estimated noise variance to generate an estimate of the overall channel estimator error, and setting the filter cutoff to minimum estimation error.

Abstract: Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: An analog-to-digital converter (ADC) is provided. The ADC includes a plurality of pipelined ADCs and an adjustment circuit. Each pipelined ADC is adapted to receive an analog input signal, has an adjustable transfer function, and includes a compensator. The adjustment circuit is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error.

Abstract: A timing skew estimation system is disclosed that includes a plurality of interleaved analog-to-digital converter circuits (ADCs), a timing mismatch estimation unit, and a correction unit. The timing mismatch estimation unit calculates a correlation between each of the plurality of ADCs. Then the timing mismatch estimation unit calculates a cost function for each of the plurality of ADCs, except the reference ADC. The timing mismatch estimation unit further calculates a gradient for each of the plurality of ADCs, except the reference ADC.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: A timing skew estimation system is disclosed that includes a plurality of interleaved analog-to-digital converter circuits (ADCs), a timing mismatch estimation unit, and a correction unit. The timing mismatch estimation unit calculates a correlation between each of the plurality of ADCs. Then the timing mismatch estimation unit calculates a cost function for each of the plurality of ADCs, except the reference ADC. The timing mismatch estimation unit further calculates a gradient for each of the plurality of ADCs, except the reference ADC.

Abstract: A method and apparatus for estimating Doppler channel in an Orthogonal Frequency-Division Multiplexor. The method includes selecting a continuation pilot, generating a channel estimation, filtering the continual pilot with at least one channel estimator, computing the error between the channel estimation and the filtered channel estimates, averaging the error across continual pilot carriers and over time, estimating noise variance, corrects average error utilizing the estimated noise variance to generate an estimate of the overall channel estimator error, and setting the filter cutoff to minimum estimation error.

Abstract: A method of estimating a channel length (304) in a wireless receiver is disclosed. The receiver receives a signal (122) from a remote transmitter. The receiver selects a plurality (K) of different candidate channel lengths and determines a respective criterion value (402) of the signal for each of the plurality of different candidate channel lengths. The receiver selects a channel length (410) from the plurality of different candidate channel lengths in response to the respective criterion value (404).