Abstract: An interface circuit and method are described, in which the interface circuit includes a plurality of bi-directional buffers and logic, responsive to a read request from a system component, configured to identify whether the requested data presently resides in the plurality of bi-directional buffers and is destined to be written from the bi-directional buffers to an external memory, wherein the logic is further configured to supply that data from the bi-directional buffers to the requesting system component, without first writing that data to the external memory.

Abstract: An interface circuit and method are described, in which the interface circuit includes a plurality of bi-directional buffers and logic, responsive to a read request from a system component, configured to identify whether the requested data presently resides in the plurality of bi-directional buffers and is destined to be written from the bi-directional buffers to an external memory, wherein the logic is further configured to supply that data from the bi-directional buffers to the requesting system component, without first writing that data to the external memory.

Abstract: This disclosure generally relates to a processor configured to access an element in a data structure. The processor includes an element in a data structure having an array, an index, and a base address. A fractional shifter is also included and is configured to shift the index value up to three bit places, and output a byte offset. An adder is configured to add the byte offset with the base address and output a final address. Further included is a general purpose shifter that is configured to rotate left and right, and shift left and right. A selector is configured to select either the final address or an output signal from the general purpose shifter.

Abstract: The present invention is generally directed to an apparatus and method for accessing registers within a processor. In accordance with one embodiment, an apparatus and method are provided for a processor in which at least two separate indicia (such as register select lines, register bank identifiers, processor mode identifiers, etc.) are utilized to uniquely identify and access a processor register. In accordance with this embodiment, bit lines of the separate indicia are encoded into a single, mapped set of signal lines, and these encoded signal lines are used to access the register.

Abstract: This disclosure generally relates to a processor configured to access of an element in a data structure. The processor includes an element in a data structure having an array, and at least one index, a base address. A fractional shifter is also included and is configured to shift the index value up to three bit places, and output a byte offset. An adder is configured to add the byte offset with the base address and output a final address. Further included is a general purpose shifter that is configured to rotate left and right, and shift left and right. A selector is configured to select either the final address or an output signal from the general purpose shifter.

Abstract: The present invention is generally directed to a method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage data transfers between processor registers that are configured to emulate a top portion of a stack and memory, which contains, the remainder of the stack. Some embodiments utilize a variable buffer that is configured to buffer transfers between the processor registers and the memory. The actual amount of data stored in the variable buffer is configured to be flexible, so that transfers between the variable buffer and processor registers are managed to keep the processor registers filled with active stack data (assuming that stack data exists). However, transfers between the variable buffer and memory may be configured to occur only when the variable buffer exceeds certain fill capacities.

Abstract: The present invention is generally directed to method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage a plurality of processor registers to store the top portion of the stack. Data is managed in these registers by managing a pointer that points to a current top-of-stack register. As data is pushed or popped from the stack, the top-of-stack point is incremented or decremented accordingly.