Abstract: A photovoltaic (PV) ac-module grounding system includes a plurality of PV dc-voltage modules. Each PV dc-voltage module is integrated with a corresponding dc-ac micro-inverter to provide a corresponding PV ac-voltage module. Each PV ac-voltage module includes an ac-voltage plug and play connector that includes a dc ground conductor. Each dc-ac micro-inverter is internally electrically connected to its own chassis ground or metal enclosure which in turn is electrically connected to a corresponding dc ground conductor. A dc ground path is carried through an ac power bus from ac-voltage module to ac-voltage module through the plug and play connectors via the dc ground conductors.

Abstract: The solar cell comprises a front side comprising a first doped layer, a backside comprising formations defining channels therebetween, the backside further comprising a second doped layer situated on at least some of the surfaces of the channels facing the front side, and an electrically conductive layer situated on at least some surfaces of the channels facing the front side. The first and second doped layers comprise opposite polarity types.

Abstract: A deployable solar panel system includes a plurality of solar cell panels that are mechanically and electrically coupled to each other prior to shipment to an installation site, folded in a stacking arrangement within a packaging container for shipment to the installation site, and then unfolded to deploy the solar cell panels at a desired tilt angle during installation at the installation site. In one embodiment, the solar cell panels are mechanically coupled to each other using a hinge assembly, such as a hinge bracket and hinge pin. Each solar cell panel system is electrically coupled to each other using a series string. The series string may be electrically coupled to a DC-DC converter and/or a DC-AC inverter.

Abstract: A photovoltaic framed module array apparatus for mounting a first framed photovoltaic (PV) module and a second framed PV module is provided. The photovoltaic framed module array apparatus comprises a first rail. The first rail includes an insert slot for accommodating an insert edge of the first framed PV module, and a capture slot for accommodating a capture edge of the second framed PV module. The capture slot is positioned substantively parallel to the insert slot.

Abstract: A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.

Abstract: The solar cell comprises a front side comprising a first doped layer, a backside comprising formations defining channels therebetween, the backside further comprising a second doped layer situated on at least some of the surfaces of the channels facing the front side, and an electrically conductive layer situated on at least some surfaces of the channels facing the front side. The first and second doped layers comprise opposite polarity types.

Abstract: A solar energy concentrator system comprises an optically transparent component, a bifacial solar cell situated within the optically transparent component and configured to intercept sunlight, a reflective component configured to reflect un-intercepted sunlight towards the bifacial solar cell, wherein the bifacial cell is configured to be positioned with a first surface facing sunlight and a second surface facing the reflective component.

Abstract: A structural building component for a residential or light commercial building includes a PV laminate and a plastic frame disposed at least around the PV laminate. The plastic frame includes a first electrical connector for communication with the PV laminate and receptive to electrical connection with a contiguous PV laminate. The first electrical connector is configured to facilitate electrical and mechanical connection with the contiguous PV laminate and the frame includes a means for facilitating attachment to the building structure.

Abstract: A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.

Abstract: An imaging system is disclosed that includes a first imaging panel and a second imaging panel disposed about an imaging volume. The imaging panels may be configured to image the entire imaging volume and may include panels using any form of acoustic or electromagnetic energy such as ultrasound panels, optical panels, electrical impedance panels, field emitter/x-ray detector panels, or a combination thereof. In one embodiment, a first group of sensors are included in a 2D matrix of sensors configured to transmit ultrasound through the imaging volume to a second group of sensors included in a second 2D matrix of sensors and vice versa. In a second embodiment the system may further include a second imaging system having a transmitter, a receiver, or both, disposed adjacent the first imaging panel, the second imaging panel, or both. A third embodiment may include at least one additional imaging panel.

Abstract: A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

Abstract: A method of power electronic packaging includes a practicable and reliable method of fabricating power circuit modules and associated connections that are compatible with the standard top layer metalization of commercially available power devices. A planar single- or multi-layer membrane structure is attached to a carrier frame, and a via pattern is formed in the membrane. Power devices are aligned and attached to the planar membrane structure; a top layer interconnect structure is formed by metalizing the vias and the film; and a circuit is formed by patterning a deposited metal layer. The carrier frame is removed, and upper and lower thermal base plate sub-assemblies are attached to the power device-on-membrane structure. The planar device-on-membrane structure accommodates different types of power devices having variations in thickness. The thermal base plate sub-assemblies may include integral, high-performance heat exchangers for providing a low thermal resistance path to the ambient.

Abstract: A power semiconductor device package includes at least one power semiconductor device mounted onto at least one electrically and thermally conductive spacer having an upper end surface bonded to a back surface of the device; a substrate of hardened substrate molding material surrounding the semiconductor device and the spacer except for an active major surface of the device and an lower end surface of the spacer, a dielectric film overlying the device active major surface and a top side of the substrate, the dielectric layer having a plurality of holes aligned with predetermined ones of the contact pads; a top side patterned metal layer on the dielectric film including portions extending into the holes electrically and thermally connected to contact pads of the device; and a backside metal layer on a substrate bottom side electrically and thermally connected to the spacer lower end surface.

Abstract: A method of power electronic packaging includes a practicable and reliable method of fabricating power circuit modules and associated connections that are compatible with the standard top layer metalization of commercially available power devices. A planar single- or multi-layer membrane structure is attached to a carrier frame, and a via pattern is formed in the membrane. Power devices are aligned and attached to the planar membrane structure; a top layer interconnect structure is formed by metalizing the vias and the film; and a circuit is formed by patterning a deposited metal layer. The carrier frame is removed, and upper and lower thermal base plate sub-assemblies are attached to the power device-on-membrane structure. The planar device-on-membrane structure accommodates different types of power devices having variations in thickness. The thermal base plate sub-assemblies may include integral, high-performance heat exchangers for providing a low thermal resistance path to the ambient.

Abstract: A FET package including one or more FETs includes an arrangement of three metallization layers for the gate, drain, and source terminals thereof. The layers include a gate runner metallizaton layer that allows the FETs to be arranged in a parallel manner so as to reduce the overall total on-state resistance to an optimum value, while allowing the gate switching capacitance to be increased to an optimized value. The gate runner metallization layer is arranged to minimize the overlapping capacitance between the gate and source terminals and between the gate and drain terminals. Additional semiconductor devices may be incorporated into the FET package using additional terminals interconnected through the metallization layers, thus providing additional functions.

Abstract: Matrix filters useful in low-noise power distribution systems include arrays of capacitors and inductors with interleaved interconnections in an high density interconnect structure so as to achieve nearly ideal performance, i.e., such that capacitor and inductor parasitics are minimized. The matrix filters are bi-directional which help to isolate different load modules by attenuating the switching noise of associated power converters as well as the noise generated by digital loads.

Abstract: A magnetic or electromagnetic circuit component includes an embedded magnetic material (e.g., ferromagnetic) in an HDI structure with alternating dielectric and metal or winding layers. In one embodiment, the ferromagnetic material is situated in a substrate well, or cavity, with or without an adhesive. Alternatively, the ferromagnetic material is co-fired with the ceramic substrate and then machined to achieve a required core shape. An electroplating process is employed to construct the metal layers, such process including differential plating for varying the thickness of metal layers and/or other portions of the circuit. Laser ablation or any other suitable technique is employed to make through-holes for insertion of the posts of a ferromagnetic core plate used to complete a magnetic circuit, if required. Advantageously, a magnetic or electromagnetic component may have a height of less than about 0.1 inch.