Abstract: Simulator based detection of a violation of a coherency protocol in an incoherent shared memory system is disclosed. One example is a system including a simulator running on a first computing system, where the simulator simulates a second computing system that is a target for an application to be tested, and where the simulator includes a cache manager to monitor a state of a plurality of simulated caches in an incoherent memory system shared by a plurality of simulated processors, wherein the plurality of simulated processors simulate operations of a respective plurality of processors of the second computing system, and detect a violation of a coherency protocol in the shared memory system, and an alert generator to provide, via a computing device on the first computing system, an alert indicative of the violation.

Abstract: A memory region has logical partitions. Each logical partition has data packages. The memory region discontiguously stores the data packages of the logical partitions. A writing process can discontiguously generate the data packages of the logical partitions. A reading process can contiguously retrieve the data packages of a selected logical partition.

Abstract: Examples disclosed herein relate to a hierarchical file system. The hierarchical file system may include a first and a second virtual file referencing a stored data set. The first virtual file may include a set of first keys of a first level of specificity, with each key of the set of first keys including a record locator. The second virtual file may include a set of second keys referencing the data set and of a second level of specificity. The set of first keys within the first virtual file is searched in response to a query for data of the data set. A key from the set of second keys is accessed via the record locator from a key from the set of first keys where the data of the data set was not identified by the set of first keys.

Abstract: Systems and methods associated with computing cluster synchronization are disclosed. One example method includes periodically requesting timing values from a set of notes in a computing cluster. The method also includes receiving timing values from members of the set of nodes. The method also includes providing a synchronization value to members of the set of nodes. The synchronization value may be generated based on the timing values. Additionally, the synchronization value may be used to order events across the members.

Abstract: Simulator based detection of a violation of a coherency protocol in an incoherent shared memory system is disclosed. One example is a system including a simulator running on a first computing system, where the simulator simulates a second computing system that is a target for an application to be tested, and where the simulator includes a cache manager to monitor a state of a plurality of simulated caches in an incoherent memory system shared by a plurality of simulated processors, wherein the plurality of simulated processors simulate operations of a respective plurality of processors of the second computing system, and detect a violation of a coherency protocol in the shared memory system, and an alert generator to provide, via a computing device on the first computing system, an alert indicative of the violation.

Abstract: Examples include a system comprising a non-volatile memory, a cluster management interface, and a multi-node cluster. In some examples, the cluster management interface may monitor a system critical alert to determine if the system critical alert has been triggered. Based on the determination that it has been triggered, the cluster management interface may multicast a system failure notification. The multi-node cluster of the system has multiple nodes, each node connected to the non-volatile memory and having a processor and a processor cache. Each node of the multi-node cluster may determine if the system failure notification has been received and based on the determination that it has been received, each node may freeze execution of all processes on the process and flush the processor cache to the non-volatile memory.

Abstract: Examples include a system comprising a non-volatile memory, a cluster management interface, and a multi-node cluster. In some examples, the cluster management interface may monitor a system critical alert to determine if the system critical alert has been triggered. Based on the determination that it has been triggered, the cluster management interface may multicast a system failure notification. The multi-node cluster of the system has multiple nodes, each node connected to the non-volatile memory and having a processor and a processor cache. Each node of the multi-node cluster may determine if the system failure notification has been received and based on the determination that it has been received, each node may freeze execution of all processes on the process and flush the processor cache to the non-volatile memory.

Abstract: Systems and methods associated with computing cluster synchronization are disclosed. One example method includes periodically requesting timing values from a set of notes in a computing cluster. The method also includes receiving timing values from members of the set of nodes. The method also includes providing a synchronization value to members of the set of nodes. The synchronization value may be generated based on the timing values. Additionally, the synchronization value may be used to order events across the members.

Abstract: A computing system can include a processor to execute stored instructions and a memory that stores instructions. The memory can include computer-implemented code to receive a structured query language (SQL) query requesting data from a non-structured query language (NoSQL) database. The memory can also include computer-implemented code to identify a query qualification and a related table in a NoSQL database. The memory can further include computer-implemented code to determine a row iterator class and computer-implemented code to access the identified related table. Additionally, the memory can include computer-implemented code to return the requested data.

Abstract: A Registration protocol is used in transaction processing for normal operations. If an error occurs, the system reverts to a Full Broadcast protocol. The Registration Protocol reduces the number of messages that are sent among CPUs in a cluster thereby permitting performance improvements in the system. The Registration Protocol has Begin, DP2 Check, Phase 1 Flush and Phase 2 (lock release) phases just as does the Full Broadcast Protocol, thereby permitting the Full Broadcast protocol to step in at any phase after an error is detected.

Abstract: A modified transaction registration protocol is disclosed. The registration protocol is inherently centralized in that processes requesting registration to participate in the work of a transaction, must send a request to a Broadcast Owner CPU which is the CPU that initiated the transaction. The processes wait, suspended, until a response is received from the Broadcast Owner CPU. However, if the Broadcast Owner CPU fails to respond to the registration request, then the processes that are waiting are incapable performing work for the transaction. While a CPU failure may not occur often, in a fault-tolerant system, such events must be accounted for. Therefore, the transaction registration protocol is modified to revert to a Full Broadcast transaction protocol and complete any outstanding registration requests. This is accomplished by distributing transactions to all of the CPUs in the system, and in each CPU forcing the completion of registration requests in each CPU.

Abstract: A Registration protocol is used in transaction processing for normal operations. If an error occurs, the system reverts to a Full Broadcast protocol. The Registration Protocol reduces the number of messages that are sent among CPUs in a cluster thereby permitting performance improvements in the system. The Registration Protocol has Begin, DP2 Check, Phase 1 Flush and Phase 2 (lock release) phases just as does the Full Broadcast Protocol, thereby permitting the Full Broadcast protocol to step in at any phase after an error is detected.

Abstract: A modified transaction registration protocol is disclosed. The registration protocol is inherently centralized in that processes requesting registration to participate in the work of a transaction, must send a request to a Broadcast Owner CPU which is the CPU that initiated the transaction. The processes wait, suspended, until a response is received from the Broadcast Owner CPU. However, if the Broadcast Owner CPU fails to respond to the registration request, then the processes that are waiting are incapable performing work for the transaction. While a CPU failure may not occur often, in a fault-tolerant system, such events must be accounted for. Therefore, the transaction registration protocol is modified to revert to a Full Broadcast transaction protocol and complete any outstanding registration requests. This is accomplished by distributing transactions to all of the CPUs in the system, and in each CPU forcing the completion of registration requests in each CPU.