Patents by Inventor Charles Synder

Charles Synder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7476329
    Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: January 13, 2009
    Assignee: EverSpin Technologies, Inc.
    Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Kelly Kyler, Charles A. Synder, Kenneth H. Smith, Clarence J. Tracy, Richard Williams
  • Publication number: 20050130374
    Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
    Type: Application
    Filed: February 2, 2005
    Publication date: June 16, 2005
    Inventors: Gregory Grynkewich, Brian Butcher, Mark Durlam, Kelly Kyler, Charles Synder, Kenneth Smith, Clarence Tracy, Richard Williams
  • Patent number: 6881351
    Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: April 19, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Kelly Kyler, Charles A. Synder, Kenneth H. Smith, Clarence J. Tracy, Richard Williams
  • Publication number: 20040211749
    Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 28, 2004
    Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Kelly Kyler, Charles A. Synder, Kenneth H. Smith, Clarence J. Tracy, Richard Williams