Abstract: The Spread Spectrum Image Steganography (SSIS) of the present invention is a data hiding/secret communication steganographic system which uses digital imagery as a cover signal. SSIS provides the ability to hide a significant quantity of information bits within digital images while avoiding detection by an observer. The message is recovered with low error probability due the use of error control coding. SSIS payload is, at a minimum, an order of magnitude greater than of existing watermarking methods. Furthermore, the original image is not needed to extract the hidden information. The proposed recipient need only possess a key in order to reveal the secret message. The very existence of the hidden information is virtually undetectable by human or computer analysis. Finally, SSIS provides resiliency to transmission noise, like that found in a wireless environment and low levels of compression.

Abstract: Microinstruction selection circuitry effects the selection of successive microinstructions of a sequence. Current and next PCs are stored in first and second registers. Current PC is provided to a memory from one register to fetch a current instruction from memory while a next PC is generated and stored in the other register. At end of a current instruction, next PC becomes current PC and a new next PC is generated and stored in the register previously storing the former current PC.

Abstract: A computer system architecture includes a processor for processing data, a memory for storing at least macroinstructions for use by the processor, microinstruction logic for storing and providing sequences of frequently used microinstructions, and busses for transmitting at least macroinstructions between the processor and memory. Microinstruction memory circuitry stores microinstructions in segmented form in available microinstruction memory space. Microinstruction segment by segment selection circuitry effects the selection of successive microinstructions of sequences of microinstructions.

Abstract: Memory control circuitry is disclosed for providing memory refresh during battery back-up operation. Memory addressing circuitry is connected between circuitry, such as a processor, providing memory refresh addresses, and memory addressing inputs. During normal main power supply operation, refresh addresses are provided to the memory from the processor. Upon occurrence of a main power supply failure, and start of battery back-up operation, the last refresh address provided by the processor is stored in the memory addressing circuitry and successively incremented to provide refresh addresses to the memory .