Patents by Inventor Charles Thomas Black
Charles Thomas Black has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10126652Abstract: This disclosure provides embodiments of an approach that enforces coexistence of multiple, aligned block copolymer morphologies within a single patterning layer.Type: GrantFiled: September 19, 2016Date of Patent: November 13, 2018Assignee: Brookhaven Science Associates, LLCInventors: Charles Thomas Black, Aaron Stein, Gwen Wright, Kevin G. Yager
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Publication number: 20170108778Abstract: This disclosure provides embodiments of an approach that enforces coexistence of multiple, aligned block copolymer morphologies within a single patterning layer.Type: ApplicationFiled: September 19, 2016Publication date: April 20, 2017Inventors: Charles Thomas Black, Aaron Stein, Gwen Wright, Kevin G. Yager
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Patent number: 7745863Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: June 26, 2008Date of Patent: June 29, 2010Assignee: International Business Machines CorporationInventors: James W. Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Publication number: 20080258194Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: ApplicationFiled: June 26, 2008Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 7402857Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: March 16, 2007Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: James W. Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 7217969Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: March 7, 2003Date of Patent: May 15, 2007Assignee: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 7186573Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: October 31, 2005Date of Patent: March 6, 2007Assignee: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 6773982Abstract: An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.Type: GrantFiled: August 10, 2001Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: Charles Thomas Black, Cyril Cabral, Jr., Alfred Grill, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Publication number: 20030155598Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: ApplicationFiled: March 7, 2003Publication date: August 21, 2003Applicant: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 6555859Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: August 8, 2001Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Publication number: 20020074581Abstract: An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.Type: ApplicationFiled: August 10, 2001Publication date: June 20, 2002Applicant: International Business Machines CorporationInventors: Charles Thomas Black, Cyril Cabral, Alfred Grill, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 6388285Abstract: An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.Type: GrantFiled: June 4, 1999Date of Patent: May 14, 2002Assignee: International Business Machines CorporationInventors: Charles Thomas Black, Cyril Cabral, Jr., Alfred Grill, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Publication number: 20020028549Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: ApplicationFiled: August 8, 2001Publication date: March 7, 2002Applicant: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 6333202Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: August 26, 1999Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Publication number: 20010045595Abstract: The present invention proposes a new type of single-transistor memory device, which stores information using the polarization of a ferroelectric material. The device is a floating-gate FET, with a ferroelectric material positioned between the gate and the floating gate, and a resistance, preferably in the form of a thin SiO2 dielectric between the floating gate and the transistor channel. Unlike previous designs, in this device the floating gate is both capacitively and resistively coupled to the transistor channel, which enables the device to be both read and written using low voltages. This device offers significant advantages for operation at low voltages and at high speeds, for repeated cycling of over 1010 times, since device durability is limited by the ferroelectric endurance rather than oxide breakdown, and for integration at gigabit densities.Type: ApplicationFiled: October 25, 1999Publication date: November 29, 2001Inventors: CHARLES THOMAS BLACK, JEFFREY JOHN WELSER
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Patent number: 6069381Abstract: The present invention proposes a new type of single-transistor memory device, which stores information using the polarization of a ferroelectric material. The device is a floating-gate FET, with a ferroelectric material positioned between the gate and the floating gate, and a resistance, preferably in the form of a thin SiO.sub.2 dielectric between the floating gate and the transistor channel. Unlike previous designs, in this device the floating gate is both capacitively and resistively coupled to the transistor channel, which enables the device to be both read and written using low voltages. This device offers significant advantages for operation at low voltages and at high speeds, for repeated cycling of over 10.sup.10 times, since device durability is limited by the ferroelectric endurance rather than oxide breakdown, and for integration at gigabit densities.Type: GrantFiled: September 15, 1997Date of Patent: May 30, 2000Assignee: International Business Machines CorporationInventors: Charles Thomas Black, Jeffrey John Welser
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Patent number: 5998292Abstract: The present invention relates to a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below. Specifically, the method of the present invention comprises etching at least one hole, defined by walls, at least partly through a semiconducting material; forming a layer of electrically insulating material to cover said walls; and forming an electrically conductive material on said walls within the channel of the hole. Microelectronic devices containing the micro-post wiring of the present invention are also disclosed herein.Type: GrantFiled: November 12, 1997Date of Patent: December 7, 1999Assignee: International Business Machines CorporationInventors: Charles Thomas Black, Joachim Norbert Burghartz, Sandip Tiwari, Jeffrey John Welser