Patents by Inventor Charles W. C. Lin

Charles W. C. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6576493
    Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip, a metal base, an insulative base and a conductive trace, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, and the conductive trace includes a contact terminal that extends through the insulative base, then forming an opening that extends through the metal base and the insulative base, exposes the pad and is spaced from the contact terminal, then forming a connection joint that contacts and electrically connects the conductive trace and the pad, and then removing a portion of the metal base that contacts the contact terminal. Preferably, the opening extends through an insulative adhesive that attaches the chip to the conductive trace.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: June 10, 2003
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Cheng-Lien Chiang
  • Patent number: 6562709
    Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes an insulative base and a conductive trace. The conductive trace includes a pillar and a routing line. An electroplated contact terminal contacts the pillar, and an electroplated connection joint contacts the routing line and the pad. A method of manufacturing the assembly includes simultaneously electroplating the contact terminal and the connection joint.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: May 13, 2003
    Inventor: Charles W. C. Lin
  • Patent number: 6562657
    Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes an insulative base, a conductive trace and a through-hole between its top and bottom surfaces. The through-hole includes a top sidewall portion adjacent to the top surface and a bottom sidewall portion adjacent to the bottom surface. The conductive trace includes a pillar at the top surface and a routing line at the bottom sidewall portion. An electrolessly plated contact terminal on the pillar extends above the base, and an electrolessly plated connection joint in the through-hole connects the routing line and the pad. Preferably, the connection joint is the only metal in the through-hole. A method of manufacturing the assembly includes simultaneously electrolessly plating the contact terminal and the connection joint.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: May 13, 2003
    Inventor: Charles W. C. Lin
  • Patent number: 6551861
    Abstract: A method of manufacturing a semiconductor chip assembly includes providing a semiconductor chip that includes a conductive pad, and providing a support circuit that includes an insulative base, a conductive trace and a through-hole that extends through the conductive trace and is covered by the base. One embodiment includes disposing an adhesive beneath the through-hole, mechanically attaching the chip to the support circuit using the adhesive such that a portion of the pad is directly beneath the through-hole, and then applying an etch to form openings in the base and the adhesive such that the openings and the through-hole expose the pad. Another embodiment includes disposing an adhesive beneath the through-hole, applying an etch to form openings in the base and the adhesive, and then mechanically attaching the chip to the support circuit using the adhesive such that the openings and the through-hole expose the pad.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: April 22, 2003
    Inventor: Charles W. C. Lin
  • Patent number: 6548393
    Abstract: A semiconductor chip assembly includes a semiconductor chip, a conductive trace, an insulative adhesive and a hardened connection joint. The conductive trace includes first and second opposing surfaces and a peripheral sidewall between the surfaces, the first surface faces away from the pad and the peripheral sidewall overlaps the pad. The adhesive is between the second surface and the pad. The connection joint contacts the first surface, the peripheral sidewall and the pad, extends between the peripheral sidewall and the pad and electrically connects the conductive trace and the pad. Preferably, the connection joint is reflowed solder or cured conductive adhesive. A method of manufacturing the assembly includes disposing the adhesive between the conductive trace and the pad, then etching the adhesive thereby exposing the pad, then depositing a non-solidified material on the first surface, the peripheral sidewall and the pad, and then transforming the non-solidified material into the connection joint.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: April 15, 2003
    Inventor: Charles W. C. Lin
  • Patent number: 6544813
    Abstract: A method of manufacturing a semiconductor chip assembly includes providing a semiconductor chip and a conductive metal, wherein the chip includes a conductive pad and the conductive metal includes routing line that is disposed above and overlaps the pad, etching the conductive metal on a side opposite the routing line to expose the routing line, and forming a connection joint that contacts and electrically connects the routing line and the pad.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: April 8, 2003
    Inventor: Charles W. C. Lin
  • Patent number: 6537851
    Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the conductive trace includes a bumped terminal, the base includes a recess, the conductive trace is disposed proximate to the pad, the base contacts and covers the conductive trace on a side opposite the chip, the bumped terminal is in the recess, and the conductive trace and the base are different metals, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is outside a periphery of the chip, and an encapsulant provides compressible mechanical support for the bumped terminal.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: March 25, 2003
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Cheng-Lien Chiang
  • Patent number: 6511865
    Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes a conductive trace. A ball bond contacts and electrically connects the conductive trace and the pad. A method of manufacturing the assembly includes mechanically attaching the chip to the support circuit and then forming the ball bond using thermocompression or thermosonic wire bonding.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: January 28, 2003
    Inventor: Charles W. C. Lin
  • Patent number: 6509639
    Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, and the pillars are disposed outside the peripheries of the chips and aligned with one another. The conductive bond contacts and electrically connects the pillars.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: January 21, 2003
    Inventor: Charles W. C. Lin
  • Patent number: 6492252
    Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the base includes a recess, the conductive trace includes a bumped terminal in the recess, the bumped terminal includes a cavity that extends into and faces away from the recess, the base contacts and covers the conductive trace on a side opposite the chip, and the conductive trace and the base are different metals, mechanically attaching the chip to the conductive trace using an insulative adhesive that extends into the cavity, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is inside a periphery of the chip, and the adhesive fills the cavity.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: December 10, 2002
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Cheng-Lien Chiang
  • Patent number: 6451626
    Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, and the pillars are disposed outside the peripheries of the chips and aligned with one another. The conductive bond contacts and electrically connects the pillars.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: September 17, 2002
    Inventor: Charles W.C. Lin
  • Publication number: 20020127772
    Abstract: A flip chip assembly, and methods of forming the same, including a single or multi-layer substrate having a plurality of via holes which serve as the connection between the semiconductor device and substrate circuitry. The method of manufacturing the flip chip assembly includes the steps of attaching an integrated circuit (IC) chip having a plurality of input/output terminal pads to a rigid or flexible substrate having a plurality of via holes. The via holes are aligned with the terminal pads so that the respective traces on the substrate can be connected to the respective terminal pads through the via holes. After attachment, the pre-deposited solder inside the via holes or on the terminal pads is re-flowed. This re-flow soldering process electrically connects the IC chip to the substrate. The solder can be deposited by plating, wave soldering, meniscus coating, and screen printing techniques.
    Type: Application
    Filed: May 10, 2001
    Publication date: September 12, 2002
    Applicant: Charles W.C. Lin.
    Inventor: Charles W.C. Lin
  • Publication number: 20020125581
    Abstract: A flip chip assembly, and methods of forming the same, including a single or multi-layer substrate having a plurality of via holes which serve as the connection between the semiconductor device and substrate circuitry. The method of manufacturing the flip chip assembly includes the steps of attaching an integrated circuit (IC) chip having a plurality of input/output terminal pads to a rigid or flexible substrate having a plurality of via holes. The via holes are aligned with the terminal pads so that the respective traces on the substrate can be connected to the respective terminal pads through the via holes. After attachment, the pre-deposited solder inside the via holes or on the terminal pads is re-flowed. This re-flow soldering process electrically connects the IC chip to the substrate. The solder can be deposited by plating, wave soldering, meniscus coating, and screen printing techniques.
    Type: Application
    Filed: May 10, 2001
    Publication date: September 12, 2002
    Applicant: Charles W.C. Lin.
    Inventor: Charles W.C. Lin
  • Patent number: 6448644
    Abstract: A flip chip assembly, and methods of forming the same, including a single layer or multilayer substrate in which via holes serve as connections between a semiconductor chip and the substrate. The assembling steps comprise attaching an integrated circuit chip to a rigid or flexible dielectric substrate having a plurality of via holes for connecting respective traces on the substrate with respective input/output terminal pads of the integrated circuit chip. The via holes are aligned and placed on top of the pads so that the pads are totally or partially exposed through the opposite side of the substrate. Electrically conductive material is subsequently deposited in the via holes as well as on the surface of the pads to provide electrical connections between the integrated circuit chip and the traces of the dielectric circuitry.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: September 10, 2002
    Inventor: Charles W. C. Lin
  • Patent number: 6448108
    Abstract: A method of manufacturing a semiconductor chip assembly includes providing a semiconductor chip and a conductive metal, wherein the chip includes a conductive pad, the conductive metal includes a dimple, and the pad is aligned with the dimple, etching the conductive metal on a side opposite the dimple such that the dimple forms a through-hole in the conductive metal, and forming a connection joint in the through-hole that electrically connects the conductive metal and the pad. The method may include mechanically attaching the chip to the conductive metal using an adhesive before forming the through-hole, and forming an opening in the adhesive directly beneath the through-hole thereby exposing the pad after mechanically attaching the chip to the conductive metal and before forming the connection joint.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: September 10, 2002
    Inventor: Charles W. C. Lin
  • Patent number: 6444489
    Abstract: A semiconductor chip assembly includes a semiconductor chip and a molded substrate. The chip includes a conductive pad. The molded substrate includes a base, a bump that extends above the base, and a through-hole in the base that is offset from the bump and aligned with the pad. A routing line covers the bump and extends along a top surface of the molded substrate to the through-hole and extends through the through-hole and contacts the pad. The molded substrate is compressible and permits a portion of the routing line that covers the bump to exhibit elastic deformation in response to vertically oriented external pressure. A method of manufacturing the assembly includes forming the molded substrate and attaching the molded substrate to the chip by transfer molding, exposing the pad using the through-hole, depositing a metal layer on the molded substrate and in the through-hole and on the pad, and removing a portion of the metal layer to form the routing line.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: September 3, 2002
    Inventor: Charles W. C. Lin
  • Patent number: 6440835
    Abstract: A method of connecting a conductive trace to a semiconductor chip includes aligning a conductive pad on the chip with a through-hole in the conductive trace while a base covers the through-hole on a side opposite the chip wherein the conductive trace and the base are different materials, removing some or all of the base thereby exposing the through-hole, and forming a connection joint in the through-hole that electrically connects the conductive trace and the pad. The method may include electroplating the conductive trace onto the base, mechanically attaching the chip to the conductive trace using an adhesive after aligning the pad and the through-hole and before removing some or all of the base, and forming an opening in the adhesive directly beneath the through-hole thereby exposing the pad after removing some or all of the base and before forming the connection joint.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: August 27, 2002
    Inventor: Charles W. C. Lin
  • Patent number: 6436734
    Abstract: A method of manufacturing a support circuit includes providing a conductive layer with top and bottom surfaces,,providing a top etch mask on the top surface that includes an opening that exposes a portion of the top surface, providing a bottom etch mask on the bottom surface that includes an opening that exposes a portion of the bottom surface, applying an etch to the exposed portion of the top surface through the opening in the top etch mask, thereby etching partially but not completely through the conductive layer and forming a recessed portion in the conductive layer below the top surface, forming an insulative base on the recessed portion without forming the insulative base on the top surface, and applying an etch to the exposed portion of the bottom surface through the opening in the bottom etch mask, thereby forming a routing line in the recessed portion that extends to and is covered by the insulative base.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: August 20, 2002
    Inventor: Charles W. C. Lin
  • Publication number: 20020076911
    Abstract: A semiconductor chip assembly includes a semiconductor chip and a molded substrate. The chip includes a conductive pad. The molded substrate includes a base, a bump that extends above the base, and a through-hole in the base that is offset from the bump and aligned with the pad. A routing line covers the bump and extends along a top surface of the molded substrate to the through-hole and extends through the through-hole and contacts the pad. The molded substrate is compressible and permits a portion of the routing line that covers the bump to exhibit elastic deformation in response to vertically oriented external pressure. A method of manufacturing the assembly includes forming the molded substrate and attaching the molded substrate to the chip by transfer molding, exposing the pad using the through-hole, depositing a metal layer on the molded substrate and in the through-hole and on the pad, and removing a portion of the metal layer to form the routing line.
    Type: Application
    Filed: December 15, 2000
    Publication date: June 20, 2002
    Inventor: Charles W.C. Lin
  • Patent number: 6406939
    Abstract: A flip chip assembly, and methods of forming the same, including a single layer or multilayer substrate in which via holes serve as connections between a semiconductor chip and the substrate. The assembling steps comprise attaching a chip to a substrate having a plurality of via holes for connecting respective traces on the substrate with respective input/output terminal pads of the chip. The via holes are aligned with and placed on top of the pads so that the pads are exposed through the opposite side of the substrate. Electrically conductive material is subsequently deposited in the via holes as well as on the surface of the pads to provide electrical connections between the pads and the traces. Electrically conductive materials include electroless plated metals, electrochemical plated metals, solders, epoxies and conductive polymers.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: June 18, 2002
    Inventor: Charles W. C. Lin