Abstract: An interconnect substrate mainly includes a first wiring layer, vertical connecting elements, a stress modulator, a buffering layer and a resin layer. The resin layer bonds sidewalls of the stress modulator and lateral surface of the vertical connecting elements laterally surrounding the stress modulator. The first wiring layer includes interconnect pads in the buffering layer and routing traces in the resin layer. The routing traces are integrated with the interconnect pads and electrically coupled to the vertical connecting elements. The interconnect pads are superimposed over and spaced from the stress modulator by the buffering layer, so that bumps for device connection can be mounted at the area covered by the stress modulator, thereby avoiding cracking of the bumps.

Abstract: A wiring board includes an electronic component laterally surrounded by a stiffener, and a third routing circuitry disposed beyond the space laterally surrounded by the stiffener and extends over the stiffener. The electronic component includes a first routing circuitry, an encapsulant, an array of vertical connecting elements and a second routing circuitry integrated together. The mechanical robustness of the stiffener can prevent the wiring board from warping. The embedded semiconductor device is electrically coupled to the first routing circuitry and surrounded by the vertical connecting elements in electrical connection with the first and second routing circuitries. The first routing circuitry provides primary fan-out routing for another semiconductor device to be assembled on the wiring board, whereas the third routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the electronic component with the stiffener.

Abstract: The wiring substrate includes a cavity and a plurality of metal leads disposed around the cavity. The metal leads are bonded with a resin compound and electrically connected to a buildup circuitry or a re-distribution layer under the cavity. The bottom of the cavity is covered by a dielectric layer of the buildup circuitry or the resin compound, and an aperture is formed through the dielectric layer of the buildup circuitry or the resin compound to be communicated with the cavity. As a result, a semiconductor device can be face-down disposed in the cavity and electrically connected to the buildup circuitry or the re-distribution layer by bonding wires extending through the aperture.

Abstract: An interconnect substrate includes vertical connection channels around a cavity. The vertical connection channels are made of a combination of metal posts and metallized vias. The cavity includes a recess in a core layer and an aperture in a stiffener. The metal posts, disposed over the top surface of the core layer, are sealed in the stiffener and are electrically connected to a buildup circuitry adjacent to the bottom surface of the core layer. The minimal height of the metal posts needed for the vertical connection can be reduced by the amount equal to the depth of the recess. The buildup circuitry is electrically connected to the metal posts through the metallized vias.

Abstract: A face-to-face semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between both opposite sides of the core base can be reduced by the amount equal to the depth of the recess. Further, the semiconductor device is face-to-face electrically coupled to another semiconductor device through a buildup circuitry therebetween.

Abstract: A package-on-package semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between two both opposite sides of the core base can be reduced by the amount equal to the depth of the recess. Further, another semiconductor device is disposed over a top surface of the core base and is electrically coupled to the semiconductor device in the dielectric recess through a buildup circuitry under a bottom surface of the core base.

Abstract: A semiconductor assembly includes an anti-warping controller, a semiconductor device, a balance layer and a first routing circuitry positioned within a through opening of a stiffener and a second routing circuitry positioned outside of the through opening of the stiffener and electrically connected to the first routing circuitry and a vertical connecting element of the stiffener. The mechanical robustness of the stiffener and the anti-warping controller can prevent the assembly from warping, whereas the vertical connecting element of the stiffener provides electrical connection between two opposite sides of the stiffener. The first routing circuitry can enlarge the pad size and pitch of the semiconductor device, whereas the second routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the first routing circuitry with the stiffener.

Abstract: A semiconductor assembly includes a face-to-face semiconductor sub-assembly electrically coupled to a circuit board by bonding wires. The face-to-face semiconductor sub-assembly includes top and bottom devices assembled on opposite sides of a routing circuitry, and is disposed in a through opening of the circuit board. The bonding wires provide electrical connections between the routing circuitry and the circuit board to interconnect the devices face-to-face assembled in the sub-assembly with the circuit board for next-level connection from two opposite sides of the circuit board.

Abstract: A method of making an interconnect substrate mainly includes steps of: providing metal posts around a stress modulator, providing a molding compound to bind the stress modulator and the metal posts, providing a crack inhibiting layer on the stress modulator and the molding compound and interfaces between the stress modulator and the molding compound, and depositing metal conductors on the crack inhibiting layer and electrically connected to the metal posts. The metal conductors have interconnect pads superimposed over the stress modulator so that bumps for device connection can be mounted at the area covered by the stress modulator, thereby avoiding cracking of the bumps.

Abstract: A thermally enhanced semiconductor assembly with three dimensional integration includes a stacked semiconductor sub-assembly electrically coupled to a wiring board by bonding wires. A heat spreader that provides an enhanced thermal characteristic for the stacked semiconductor sub-assembly is disposed in a through opening of a wiring structure. Another wiring structure disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias. The bonding wires provide electrical connections between the sub-assembly and the wiring board for interconnecting devices assembled in the sub-assembly to terminal pads provided in the wiring board.

Abstract: A face-to-face semiconductor assembly is characterized in that first and second semiconductor devices are face-to-face mounted on two opposite sides of a first routing circuitry and is further electrically connected to an interconnect board through the first routing circuitry. The interconnect board has a heat spreader to provide thermal dissipation for the second semiconductor device, and a second routing circuitry formed on the heat spreader and electrically coupled to the first routing circuitry. The first routing circuitry provides primary fan-out routing for the first and second semiconductor devices, whereas the second routing circuitry provides further fan-out wiring structure for the first routing circuitry.

Abstract: A face-to-face semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between both opposite sides of the core base can be reduced by the amount equal to the depth of the recess. Further, the semiconductor device is face-to-face electrically coupled to another semiconductor device through a buildup circuitry therebetween.

Abstract: A method of making a wiring board having a low CTE isolator incorporated in a resin core is characterized by the provision of an adhesive substantially coplanar with the metallized isolator and the metal layers on two opposite sides of the resin core at smoothed lapped top and bottom surfaces so that a metal bridge can be deposited on the adhesive at the smoothed lapped bottom surface and connect the metallized isolator with a surrounding heat spreader on the bottom surface of the resin core. In the method, routing circuitries are also deposited on the adhesive at the smoothed lapped top surface so as to provide electrical connections between contact pads on the isolator and terminal pads on the resin core.

Abstract: The wiring board includes a first routing circuitry and a second routing circuitry integrated with a leadframe. The first routing circuitry is laterally surrounded by the leadframe and can provide a first level routing for a semiconductor device disposed thereon. The second routing circuitry is disposed beyond the space laterally surrounded by the leadframe and extends over the leadframe and is electrically connected to the first routing circuitry and metal leads of the leadframe to provide a second level routing.

Abstract: A semiconductor assembly with built-in stiffener and integrated dual routing circuitries is characterized in that a semiconductor device and a first routing circuitry are positioned within a through opening of a stiffener whereas a second routing circuitry extends to an area outside of the through opening of the stiffener. The mechanical robustness of the stiffener can prevent the assembly from warping. The first routing circuitry can enlarge the pad size and pitch of the semiconductor device, whereas the second routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the first routing circuitry with the stiffener.

Abstract: A wiring board includes an electronic component laterally surrounded by a leadframe, and first and second buildup circuitries disposed beyond the space laterally surrounded by the leadframe and extending over the leadframe. The electronic component includes a first routing circuitry, an encapsulant, optionally an array of vertical connecting elements and optionally a second routing circuitry integrated together. The first routing circuitry provides primary routing for the semiconductor device, whereas the first and second buildup circuitries not only provides further routing, but also mechanically binds the electronic component with the leadframe. The leadframe provides electrical connection between the first buildup circuitry and the second buildup circuitry.

Abstract: A wiring board includes an electronic component laterally surrounded by a stiffener, and a third routing circuitry disposed beyond the space laterally surrounded by the stiffener and extends over the stiffener. The electronic component includes a first routing circuitry, an encapsulant, an array of vertical connecting elements and a second routing circuitry integrated together. The mechanical robustness of the stiffener can prevent the wiring board from warping. The embedded semiconductor device is electrically coupled to the first routing circuitry and surrounded by the vertical connecting elements in electrical connection with the first and second routing circuitries. The first routing circuitry provides primary fan-out routing for another semiconductor device to be assembled on the wiring board, whereas the third routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the electronic component with the stiffener.

Abstract: A semiconductor assembly having heat dissipation characteristics includes stacked semiconductor chips thermally conductible to a thermal pad of an interconnect substrate and electrically connected to the interconnect substrate through bonding wire. The bonding wires extending from a primary routing circuitry in between the stacked chips can accommodate the height difference between the stacked chips and the interconnect substrate. These wires can also effectively compensate for the thermal expansion mismatch between the stacked chips and the interconnect substrate, thereby allowing a higher manufacturing yield and better reliability.

Abstract: A wiring board includes an interposer and an electronic component laterally surrounded by a base board and a dielectric layer and connected to a routing circuitry. The interposer and the electronic component are inserted into a first through opening and a second through opening of the base board, respectively. The dielectric layer covers the top side of the base board and the top surface of the electronic component, and fills in gaps between the interposer and the base board and between the electronic component and the base board. The routing circuitry is deposited on the dielectric layer and electrically connected to the electronic component and a top wiring layer of the base board.

Abstract: The wiring substrate includes a cavity and a plurality of metal leads disposed around the cavity. The metal leads are bonded with a resin compound and provide horizontal and vertical routing for a semiconductor device to be disposed in the cavity. The resin compound fills in spaces between the metal leads and surrounds the cavity and provides a dielectric platform for a re-distribution layer or a build-up circuitry optionally deposited thereon.