Abstract: A multiple processor computer system features a store-into cache arrangement wherein each processor unit of the system has its own unique cache memory unit. Data operated upon by any one of the processor units is stored in the cache memory associated with that processor unit. When a thus modified block of data is required by another one of the processor units, the requested data is transferred directly to the requesting processor unit without having to first transfer the data to a shared main memory. Provision is also made for transferring data, under prescribed conditions from a cache to the main memory, but not as a precondition for transfer to a requesting processor.

Abstract: A bit-string address or a multi-bit character count is converted to a real word memory address by division by a constant value. The division is accomplished without reference to an arithmetic logic unit. Division is accomplished by means of a look-up table stored in a ROM with the quotient and remainder values being stored in the ROM. The provided address, or dividend, values are used to address the ROM to determine the quotient and remainder values corresponding thereto. When the dividend values are of a dimension larger than can be divided by a single pass at the ROM, the division is accomplished by several successive passes through the ROM to provide a succession of partial quotient values. The resulting quotient and remainder values define the proper address for the computer memory.