Abstract: A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.

Abstract: A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.

Abstract: Fin-defining spacers are formed on an array of mandrel structure. Mask material portions can be directionally deposited on fin-defining spacers located on one side of each mandrel structure, while not deposited on the other side. A photoresist layer is subsequently applied and patterned to form an opening, of which the overlay tolerance increases by a pitch of fin-defining spacers due to the mask material portions. Alternately, a conformal silicon oxide layer can be deposited on fin-defining spacers and structure-damaging ion implantation is performed only on fin-defining spacers located on one side of each mandrel structure. A photoresist layer is subsequently applied and patterned to form an opening, from which a damaged silicon oxide portion and an underlying fin-defining spacer are removed, while undamaged silicon oxide portions are not removed. An array of semiconductor fins including a vacancy can be formed by transferring the pattern into a semiconductor layer.

Abstract: A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region.

Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

Abstract: Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer.

Abstract: A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.

Abstract: A method for forming a sealed air gap for a semiconductor chip including forming a gate over a substrate; forming a sacrificial spacer adjacent to the gate; forming a first dielectric layer about the gate and the sacrificial spacer; forming a contact to the gate; substantially removing the sacrificial spacer, wherein a space is formed between the gate and the first dielectric layer; and forming a sealed air gap in the space by depositing a second dielectric layer over the first dielectric layer.

Abstract: A method of forming a semiconductor device includes defining a first type region and a second type region in a substrate, t separated by one or more inter-well STI structures; etching and filling, in at least one of the first type region and the second type region, one or more intra-well STI structures for isolating semiconductor devices formed within a same polarity well, wherein the one or more inter-well STI structures are formed at a substantially same depth with respect to the one or more intra-well STI structures; implanting, a main well region, wherein a bottom of the main well region is disposed above a bottom of the one or more inter-well and intra-well STI features; and implanting, one or more deep well regions that couple main well regions, wherein the one or more deep well regions are spaced away from the one or more inter-well STI structures.

Abstract: A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.

Abstract: A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.

Abstract: After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

Abstract: The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.

Abstract: A combination of two lithographically patterned mandrels can be employed in conjunction with sidewall spacers to provide two spacers. The two spacers may intersect each other and/or contact sidewall surfaces of each other to provide a thickness that is a sum of the thicknesses of the two spacers. Further, the two spacers may be patterned to provide various patterns. In addition, portions of at least one of the two spacers may be etched employing an etch mask. Additionally or alternately, an additional material may be selectively added to portions of one of the two spacers.

Abstract: A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.

Abstract: FinFETs and fin isolation structures and methods of manufacturing the same are disclosed. The method includes patterning a bulk substrate to form a plurality of fin structures of a first dimension and of a second dimension. The method includes forming oxide material in spaces between the plurality of fin structures of the first dimension and the second dimension. The method includes forming a capping material over sidewalls of selected ones of the fin structures of the first dimension and the second dimension. The method includes recessing the oxide material to expose the bulk substrate on sidewalls below the capping material. The method includes performing an oxidation process to form silicon on insulation fin structures and bulk fin structures with gating. The method further includes forming a gate structure over the SOI fin structures and the bulk fin structures.

Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

Abstract: A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.

Abstract: FinFETs and fin isolation structures and methods of manufacturing the same are disclosed. The method includes patterning a bulk substrate to form a plurality of fin structures of a first dimension and of a second dimension. The method includes forming oxide material in spaces between the plurality of fin structures of the first dimension and the second dimension. The method includes forming a capping material over sidewalls of selected ones of the fin structures of the first dimension and the second dimension. The method includes recessing the oxide material to expose the bulk substrate on sidewalls below the capping material. The method includes performing an oxidation process to form silicon on insulation fin structures and bulk fin structures with gating. The method further includes forming a gate structure over the SOI fin structures and the bulk fin structures.

Abstract: A combination of two lithographically patterned mandrels can be employed in conjunction with sidewall spacers to provide two spacers. The two spacers may intersect each other and/or contact sidewall surfaces of each other to provide a thickness that is a sum of the thicknesses of the two spacers. Further, the two spacers may be patterned to provide various patterns. In addition, portions of at least one of the two spacers may be etched employing an etch mask. Additionally or alternately, an additional material may be selectively added to portions of one of the two spacers.