Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.

Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.

Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device and a method of manufacture therefor. The method of manufacturing the LDMOS device includes forming an amorphous region in a semiconductor substrate between isolation structures and adjacent a gate structure, by implanting an amorphizing element, such as silicon or germanium, in the semiconductor substrate. The method further includes diffusing a channel dopant laterally in the amorphous region, to form a first portion of a channel.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: The present invention relates to an apparatus and method for polishing substrate surfaces. The method can include the steps of holding a substrate against a polishing surface and depositing slurry on the polishing surface. The method can further include the step of moving the holding device in a substantially curvilinear path relative to the polishing surface, or the step of moving the polishing surface in a substantially curvilinear path relative to the holding device. The apparatus comprises a polishing surface, a holding device for holding a substrate against the polishing surface, and a slurry supply system for depositing slurry on the polishing surface. The apparatus further includes a moving structure for moving the holding device in a substantially curvilinear path along the polishing surface, or a moving structure for moving the polishing surface in a substantially curvilinear path relative to the holding device. The substantially curvilinear path is preferably substantially a figure eight path.

Abstract: The present invention provides a method of manufacturing a semiconductor device, and a related method manufacturing an integrated circuit. In one embodiment, the method of manufacturing a semiconductor device includes creating a source/drain region between an electrode and an isolation structure located on a substrate. The method further includes implanting a dopant at a predetermined implant dopant concentration through an opening formed in a channel stop mask and located between the electrode and the isolation structure to form a channel stop between the source/drain region and the isolation structure.

Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device and a method of manufacture therefor. The method of manufacturing the LDMOS device includes forming an amorphous region in a semiconductor substrate between isolation structures and adjacent a gate structure, by implanting an amorphizing element, such as silicon or germanium, in the semiconductor substrate. The method further includes diffusing a first source/drain dopant laterally in the amorphous region to form a first portion of a channel.

Abstract: In a wafer fabrication process in which a photoresist stripper must be removed from the surface of a semiconductor wafer, the photoresist stripper is rinsed by inserting the wafer in a vessel (23, FIG. 3) filled with water and simultaneously pumping carbon dioxide and water into the vessel to cause the water to overflow the vessel. Preferably, the wafer is contained within the vessel for at least five minutes, and, during the rinsing step, the water completely fills the vessel and overflows at a rate of at least fifty percent of the volume of the vessel each minute. We have found that this method of rinsing photoresist stripper from semiconductor wafers significantly reduces or eliminates the incidence of corrosion pitting on aluminum conductors (12, FIG. 1) of the wafer (11).

Abstract: An anchor structure for fixedly securing a mobile home or trailer tongue relative to an underlying ground support is provided, wherein the organization includes respective right and left parallel legs mounted to a base arranged for subsequent mounting in a subterranean orientation relative to the associated trailer, with each leg pivotally mounting a respective right and left pivot leg and the pivot legs arranged for latching an upper and lower support plate relative to one another, wherein the upper and lower support plates each include a mirror image concave semi-cylindrical recess arranged to receive the trailer tongue therethrough. A modification of the invention includes spaced confronting members, each mounted to a central plate arranged for securement, or alternatively bedding within a cementious or other suitable base material.

Abstract: A diffusion furnace (11) includes a typical process tube (12) and an outer envelope (26) which forms an annular chamber (37) with the process tube. A heating element (29) of high purity graphite substantially surrounds the process tube within the chamber (37). Inner surfaces of the chamber (37) are made of materials such as, for example, silicon, pyrolytic graphite or quartz. Such materials are essentially free of harmful impurity elements such as iron, nickel, copper calcium or gold, which have an energy level about halfway between the valence and the conduction band of a semiconductor material to be processed within the process tube. A nonoxidizing gas within the heater chamber protects the graphite elements therein from oxidation. A small gas flow within the chamber (37) is preferred to purge such harmful impurity elements as may penetrate into the chamber during the operation of the furnace.

Abstract: In a dynamic MOS (Metal Oxide Semiconductor) random access memory, reverse bias leakage currents which deplete stored charges are reduced by minimizing minority carrier generation-type currents. By so minimizing these currents, the leakage currents become dominated by minority carrier diffusion currents. The memory is ideally formed in an upper semiconductor layer (14) of a layered structure (11). The semiconductor layer (14) is grown epitaxially with a relatively low dopant concentration on a semiconductor substrate (12) with a dopant concentration of the same conductivity type and about three orders of magnitude greater than that of the epitaxially grown layer. The epitaxially grown structure is advantageously suited for the memory circuits in that it may be formed with very low leakage currents. The material further offers by its layered structure a basis for optimizing dynamic memory device characteristics.

Abstract: To improve the control over resistivity of grown single crystalline ingots, to reduce the turn-around time between growth of successive ingots in a particular crystal grower and to enable recycling of otherwise junk material, a sample of a molten material (the "melt") from which the ingot is to be grown is withdrawn from the crystal grower, cooled, and analyzed. Based on the analysis, controlled additional amounts of the material and/or a dopant impurity are added directly to the melt to restore it to a desired chemical composition. Thus, avoidable is costly and time-consuming cooling of the melt and restarting the system with a completely new charge of material and impurity, and achievable is uniformity of resistivity among the successively grown ingots. Preferably the sample is withdrawn from the melt into a quartz tube which is inserted into the system through a port.

Abstract: A semiconductor wafer from which devices, such as transistors, integrated circuits or the like, are to be formed is gettered. This is done by directing a high energy beam, such as a laser beam, on the surface of the wafer opposite to the surface on which the devices are to be formed. The beam is absorbed by such surface and produces lattice damage and strain in the region of such surface. The wafer is then heated at a temperature and for a time sufficient to produce a dislocation array adjacent to the region of damage. This relieves the strain and attracts mobile defects in the wafer toward the array and away from the surface of the wafer on which the devices are to be formed.The beam may also be directed on the surface of the wafer where the semiconductor devices are to be formed so long as the beam avoids those portions of such surface where the devices are to be formed.