Abstract: A passive arbitration system is employed for distributed, asynchronous, collision-free packet communication access scheduling along a high speed bus medium (1). First and second monitor end stations (2,3) are provided at opposite ends of the bus medium. A first plurality of data stations (4) and a second plurality of data stations (6) are operatively connected with the bus medium. The first monitor end station broadcasts a first synchronization header (SH.sub.1) which polls the first group stations. The first group stations with no data to transmit respond to the synchronization header by blocking themselves. The one of the first group stations which has data to transmit and which first receives the first synchronization header alters it and transmits a data packet on the bus member. First group stations downstream are inhibited from transmitting by the altered first synchronization header.

Abstract: An automatic sequencing circuit is disclosed which recognizes a particular coded input signal, initiates a process or data operation, and provides a coded output indicative of the operation performed. The circuit is particularly suited to hardware implementation of the control graph of a directed-graph design for any equipment using digital logic circuits.