Patents by Inventor Charles W. Selvidge
Charles W. Selvidge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230306169Abstract: Various aspects of the present disclosed technology relate to hybrid static and dynamic switching in a reconfigurable hardware modeling circuit for flexible and low latency communications. The reconfigurable hardware modeling circuit comprises serializer circuitry and deserializer circuitry for one or more communication ports, wherein the serializer circuitry has first sub-channels for receiving data to be sent out from the reconfigurable hardware modeling circuit, and the deserializer circuitry has second sub-channels for outputting data received by the reconfigurable hardware modeling circuit.Type: ApplicationFiled: August 20, 2020Publication date: September 28, 2023Inventors: Jean-Marc Brault, Charles W. Selvidge, Jean-Paul Clavequin, Laurent Vuillemin
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Publication number: 20220329351Abstract: Each of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device comprises: a plurality of communication ports; error monitoring circuitry configured to monitor, while the reconfigurable hardware modeling device is performing an operation for verifying a circuit design, whether data received from the plurality of communication ports contain an error or not, and send out an error signal indicating the monitoring result; and rollback circuitry configured to, if data received by any of the plurality of reconfigurable hardware modeling circuits contain an error, enable the reconfigurable hardware modeling circuit to repeat the operation from a state before the error is received, and if data received by the plurality of reconfigurable hardware modeling circuits contain no error, allow the reconfigurable hardware modeling circuit to continue the operation.Type: ApplicationFiled: October 10, 2019Publication date: October 13, 2022Inventors: Charles W. Selvidge, Jean-Paul Clavequin, Jean-Marc Brault, Laurent Vuillemin
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Publication number: 20220066801Abstract: Systems and methods for emulate or prototyping of hardware, such as memory, are disclosed. A memory compiler may receive information, such as system calls, indicative of one or more aspects of latency. Responsive to the information, the memory compiler may create infrastructure, such as pipelines and FIFOs, based on the aspects of latency, for emulation or prototyping of the hardware. Using the created infrastructure may improve emulation compile speed, such as by creating a pipeline-based cache structure, and may improve emulation runtime speed, such as by utilizing earlier unused model clocks to fetch data from host sooner.Type: ApplicationFiled: July 22, 2021Publication date: March 3, 2022Inventors: Charles W. Selvidge, Mukesh Gupta, Sanjay Gupta, Suresh Krishnamurthy, Mayank Awasthi
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Patent number: 11113441Abstract: Each reconfigurable hardware modeling circuit of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device comprises: a model computation subsystem configurable either to model elements of a circuit design, or to serve as a testbench element, or both, and a network subsystem comprising: network circuitry and signal reduction circuitry, the signal reduction circuitry configurable to perform a signal reduction function, the signal reduction function combining a plurality of status signals into a single status signal, the plurality of status signals comprising status signals received from one or more reconfigurable hardware modeling circuits in the plurality of reconfigurable hardware modeling circuits. Alternatively or additionally, each network circuit of a plurality of network circuits in the reconfigurable hardware modeling device may comprise signal reduction circuitry configurable to perform the signal reduction function.Type: GrantFiled: June 25, 2020Date of Patent: September 7, 2021Assignee: Siemens Industry Software Inc.Inventors: Charles W Selvidge, Jean-Marc Brault, Jean-Paul Clavequin, Laurent Vuillemin
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Patent number: 10664566Abstract: Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device. The dispatch time information of a particular message includes information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design. The messages and the dispatch time information are sent to a traffic analysis device, which determines bandwidth information of ports of the circuit design based on the dispatch time information.Type: GrantFiled: October 24, 2017Date of Patent: May 26, 2020Assignee: Mentor Graphics CorporationInventors: Suresh Krishnamurthy, Deepak Kumar Garg, Saurabh Khaitan, Sanjay Gupta, John R. Stickley, Russell Elias Vreeland, III, Ronald James Squiers, Charles W. Selvidge
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Patent number: 10664563Abstract: A verification system comprises: a reconfigurable hardware modeling device programmed to implement a hardware model of a circuit design; a first computing unit configured to execute a first software program; and a second computing unit configured to execute a testbench model of a second software program. The execution of the first software program and the testbench model of the second software program generates first stimuli and second stimuli for an operation of the hardware model of the circuit design, respectively. The first stimuli and the second stimuli are transmitted to the hardware model of the circuit design through a communication interface.Type: GrantFiled: April 2, 2018Date of Patent: May 26, 2020Assignee: Mentor Graphics CorporationInventors: Debdutta Bhattacharya, Ayub Akbar Khan, Charles W. Selvidge
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Patent number: 10657217Abstract: Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.Type: GrantFiled: October 24, 2017Date of Patent: May 19, 2020Assignee: Mentor Graphics CorporationInventors: Suresh Krishnamurthy, Deepak Kumar Garg, Sudhanshu Jayaswal, Saurabh Khaitan, Sanjay Gupta, John R. Stickley, Russell Elias Vreeland, III, Ronald James Squiers, Abhijit Das, Charles W. Selvidge
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Patent number: 10579776Abstract: Various aspects of the present disclosed technology relate to techniques for selective conditional stall for speeding up hardware-based circuit verification. A path-breaking circuit device is inserted into a location of a design path configured to generate a stall signal indicating whether a change of signal between a pair of neighboring clock cycles of a clock signal is detected at the location. The stall signal is used to directly or indirectly suppress, when the change of signal between the pair of neighboring clock cycles is detected, the next state updating for state element models in the hardware model of circuit design. The design path is usually the critical design path. The insertion location is usually selected to be a location where the signal does not change frequently.Type: GrantFiled: October 30, 2018Date of Patent: March 3, 2020Assignee: Mentor Graphics CorporationInventors: Charles W. Selvidge, Ansuman Prusty, Vipul Kulshrestha, Kenneth W. Crouch, Matthew L. Dahl, Laurent Vuillemin
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Patent number: 10503848Abstract: An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. The part or the whole of the emulation process is then repeated with the emulator decoupled to the one or more targets. During the repeating, the input signals stored in the one or more processor-readable media are being streamed back to the emulator. The streaming in both of the capture and replay modes may be through interfaces designed for small packets of data and fast streaming speed.Type: GrantFiled: August 4, 2017Date of Patent: December 10, 2019Assignee: Mentor Graphics CorporationInventors: Krishnamurthy Suresh, Satish Kumar Agarwal, Sanjay Gupta, Charles W. Selvidge
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Patent number: 10410713Abstract: Aspects of the disclosed technology relate to techniques for modeling content-addressable memory in emulation and prototyping. A model for content-addressable memory comprises memory circuitry configured to store match results for various search keys. The match results are stored in the second memory circuitry during write operations. The model for content-addressable memory may further comprise additional memory circuitry configured to operate as a standard computer memory, performing read operations alone and write operations along with the memory circuitry.Type: GrantFiled: October 3, 2017Date of Patent: September 10, 2019Assignee: Mentor Graphics CorporationInventors: Charles W. Selvidge, Sanjay Gupta, Krishnamurthy Suresh, Praveen Shukla, Saurabh Gupta
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Publication number: 20180285484Abstract: A verification system comprises: a reconfigurable hardware modeling device programmed to implement a hardware model of a circuit design; a first computing unit configured to execute a first software program; and a second computing unit configured to execute a testbench model of a second software program. The execution of the first software program and the testbench model of the second software program generates first stimuli and second stimuli for an operation of the hardware model of the circuit design, respectively. The first stimuli and the second stimuli are transmitted to the hardware model of the circuit design through a communication interface.Type: ApplicationFiled: April 2, 2018Publication date: October 4, 2018Inventors: Debdutta Bhattacharya, Ayub Akbar Khan, Charles W. Selvidge
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Publication number: 20180113961Abstract: Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device. The dispatch time information of a particular message includes information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design. The messages and the dispatch time information are sent to a traffic analysis device, which determines bandwidth information of ports of the circuit design based on the dispatch time information.Type: ApplicationFiled: October 24, 2017Publication date: April 26, 2018Inventors: Krishnamurthy Suresh, Deepak Kumar Garg, Saurabh Khaitan, Sanjay Gupta, John R. Stickley, Russell Elias Vreeland III, Ronald James Squiers, Charles W. Selvidge
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Publication number: 20180113970Abstract: Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.Type: ApplicationFiled: October 24, 2017Publication date: April 26, 2018Inventors: Krishnamurthy Suresh, Deepak Kumar Garg, Sudhanshu Jayaswal, Saurabh Khaitan, Sanjay Gupta, John R. Stickley, Russell Elias Vreeland, III, Ronald James Squiers, Abhijit Das, Charles W. Selvidge
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Patent number: 9898563Abstract: Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.Type: GrantFiled: November 13, 2015Date of Patent: February 20, 2018Assignee: Mentor Graphics CorporationInventors: Krishnamurthy Suresh, Mukesh Gupta, Sanjay Gupta, Charles W. Selvidge
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Publication number: 20180032357Abstract: Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. The concurrent emulation system includes an emulator and an emulation control station configured to allow simultaneous emulation of multiple electronic designs. The model state module is configured to record the state of the electronic designs during emulation and the emulation trace module is configured to capture trace data associated with the emulation. A backup and capture module is also disclosed that is configured to store the recorded state and the captured trace data for use during a hardware debug process.Type: ApplicationFiled: July 10, 2017Publication date: February 1, 2018Applicant: Mentor Graphics CorporationInventors: Krishnamurthy Suresh, Charles W. Selvidge, Sanjay Gupta, Amit Jain
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Publication number: 20180011956Abstract: An emulator is configured with a circuit design model for a circuit design comprising a processor and is running with an operating system. Data are transferred from a computer to a memory in the emulator through a design-independent interface or a transaction-level interface. A software program is then activated in the emulator to enable the data to be accessed by the operating system without rebooting the emulator.Type: ApplicationFiled: July 11, 2016Publication date: January 11, 2018Inventors: Ajay Kumar, Marco Anselmo Minato, Veerendra Kandi, Charles W. Selvidge
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Publication number: 20170337309Abstract: An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. The part or the whole of the emulation process is then repeated with the emulator decoupled to the one or more targets. During the repeating, the input signals stored in the one or more processor-readable media are being streamed back to the emulator. The streaming in both of the capture and replay modes may be through interfaces designed for small packets of data and fast streaming speed.Type: ApplicationFiled: August 4, 2017Publication date: November 23, 2017Inventors: Krishnamurthy Suresh, Satish Kumar Agarwal, Sanjay Gupta, Charles W. Selvidge
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Patent number: 9767237Abstract: An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. The part or the whole of the emulation process is then repeated with the emulator decoupled to the one or more targets. During the repeating, the input signals stored in the one or more processor-readable media are being streamed back to the emulator. The streaming in both of the capture and replay modes may be through interfaces designed for small packets of data and fast streaming speed.Type: GrantFiled: November 13, 2015Date of Patent: September 19, 2017Assignee: Mentor Graphics CorporationInventors: Krishnamurthy Suresh, Satish Kumar Agarwal, Sanjay Gupta, Charles W. Selvidge
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Patent number: 9703579Abstract: Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. The concurrent emulation system includes an emulator and an emulation control station configured to allow simultaneous emulation of multiple electronic designs. The model state module is configured to record the state of the electronic designs during emulation and the emulation trace module is configured to capture trace data associated with the emulation. A backup and capture module is also disclosed that is configured to store the recorded state and the captured trace data for use during a hardware debug process.Type: GrantFiled: May 1, 2013Date of Patent: July 11, 2017Assignee: Mentor Graphics CorporationInventors: Krishnamurthy Suresh, Charles W. Selvidge, Sanjay Gupta, Amit Jain
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Publication number: 20170140083Abstract: Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.Type: ApplicationFiled: November 13, 2015Publication date: May 18, 2017Inventors: Krishnamurthy Suresh, Mukesh Gupta, Sanjay Gupta, Charles W. Selvidge