Abstract: A method for determining the correct result and the correct guard and sticky bits to obtain a more accurate result in floating point divide operations is presented. An intermediate divide result or quotient is obtained from a multiply-add hardware pipeline of a floating point processor. Remainders are calculated using the floating point numbers divided, the unit of least precision, and the unit of least precision plus one to determine where the infinitely precise result is with respect to the digital representation of the estimated quotient. Evaluating these remainders and the initial floating point numbers and comparing their signs and magnitudes leads to a selection of one of three choices as the most accurate representation of the infinitely precise result as calculated in the inventive rounding method: the intermediate result minus the unit of least precision; the intermediate divide result; or the intermediate divide result plus the unit of least precision.

Abstract: An asynchronous interface that uses vectored interface commands to reduce the latency of registered communication interface signals. In preferred embodiments, vectored commands are communicated between clock domains with handshake command signals comprising command valid and command acknowledge signals. Each command is assigned a sequential number up to a maximum number of outstanding commands. For each command number, there are a dedicated command valid and acknowledge signal pair. Command valid is sent to indicate a command is ready to be processed and acknowledge is received indicating the command is done. In preferred embodiments, each side of the asynchronous interface independently tracks the next valid/acknowledge signal pair that will be used.

Abstract: A processor receives one or more debug commands through a debug port to help debug software being executed by the processor. In response to a first one or more of the debug commands, the processor stops execution of the software, and flushes data from cache memory of the processor to one or more data locations external to the processor. In response to a second one or more of the debug commands, the processor accesses one or more data locations external to the processor, and resumes execution of the software.

Abstract: An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment mechanism is provided in the bus interface of the receiving processor to align the data transfers transparent to the receiving processor. The alignment mechanism detects an unaligned transfer in the bus command queue and forms multiple commands of aligned data to send to the processor.