Patents by Inventor Charles Walter Pearce
Charles Walter Pearce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8294210Abstract: A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.Type: GrantFiled: June 15, 2010Date of Patent: October 23, 2012Assignee: Texas Instruments IncorporatedInventors: Christopher Boguslaw Kocon, John Manning Savidge Neilson, Simon John Molloy, Haian Lin, Charles Walter Pearce, Gary Eugene Daum
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Patent number: 8288820Abstract: A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.Type: GrantFiled: June 15, 2010Date of Patent: October 16, 2012Assignee: Texas Instruments IncorporatedInventors: Christopher Boguslaw Kocon, John Manning Savidge Neilson, Simon John Molloy, Haian Lin, Charles Walter Pearce
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Publication number: 20110303976Abstract: A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.Type: ApplicationFiled: June 15, 2010Publication date: December 15, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Christopher Boguslaw KOCON, John Manning Savidge NEILSON, Simon John MOLLOY, Haian LIN, Charles Walter PEARCE, Gary Eugene DAUM
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Publication number: 20100315159Abstract: A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.Type: ApplicationFiled: June 15, 2010Publication date: December 16, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Christopher Boguslaw Kocon, John Manning Savidge Neilson, Simon John Molloy, Haian Lin, Charles Walter Pearce
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Publication number: 20090267145Abstract: A method of forming a metal-oxide-semiconductor (MOS) device includes the following steps: forming a semiconductor layer of a first conductivity type having source and drain regions of a second conductivity type, a channel region and a lightly-doped drain region formed therein; forming a gate over the channel region proximate an upper surface of the semiconductor layer; after the forming steps, depositing a first dielectric layer having a first thickness over an upper surface of the semiconductor layer; etching the first dielectric layer in a region over the lightly-doped drain proximate to the gate to reduce its thickness; conformably depositing a second dielectric layer having a second thickness over the first dielectric layer, including in the etched region, the second thickness being less than the first thickness; and forming a shielding electrode over the second dielectric layer.Type: ApplicationFiled: April 23, 2008Publication date: October 29, 2009Applicant: CICLON SEMICONDUCTOR DEVICE CORP.Inventors: Charles Walter Pearce, Simon J. Molloy, Shuming Xu, Xiao Rui Li
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Patent number: 6762457Abstract: The invention includes a laterally diffused metal oxide semiconductor transistor comprising a gate electrode and comprising tapered oxide self aligned to the gate electrode.Type: GrantFiled: November 20, 2002Date of Patent: July 13, 2004Assignee: Agere Systems Inc.Inventors: Charles Walter Pearce, Muhammed Ayman Shibib
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Publication number: 20030100165Abstract: The invention includes a laterally diffused metal oxide semiconductor transistor comprising a gate electrode and comprising tapered oxide self aligned to the gate electrode and a method of making the transistor.Type: ApplicationFiled: November 20, 2002Publication date: May 29, 2003Inventors: Charles Walter Pearce, Muhammed Ayman Shibib
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Patent number: 6552381Abstract: A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.Type: GrantFiled: February 5, 2002Date of Patent: April 22, 2003Assignee: Agere Systems, Inc.Inventors: Sailesh Chittipeddi, Charles Walter Pearce, Pradip Kumar Roy
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Patent number: 6506641Abstract: The invention includes a laterally diffused metal oxide semiconductor transistor comprising a gate electrode and comprising tapered oxide self aligned to the gate electrode and a method of making the transistor.Type: GrantFiled: August 17, 2000Date of Patent: January 14, 2003Assignee: Agere Systems Inc.Inventors: Charles Walter Pearce, Muhammed Ayman Shibib
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Patent number: 6503841Abstract: The invention includes a method of etching silicon dioxide, comprising doping a layer of silicon dioxide to form a layer of doped silicon dioxide and etching the doped silicon dioxide layer with phosphoric acid.Type: GrantFiled: July 7, 2000Date of Patent: January 7, 2003Assignee: Agere Systems Inc.Inventors: Robert William Criscuolo, Charles Walter Pearce
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Patent number: 6482694Abstract: An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer.Type: GrantFiled: June 11, 2001Date of Patent: November 19, 2002Assignee: Agere Systems, Inc.Inventors: Sailesh Chittipeddi, Charles Walter Pearce
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Publication number: 20020094653Abstract: A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.Type: ApplicationFiled: February 5, 2002Publication date: July 18, 2002Applicant: Agere Systems Guardian Crop.Inventors: Sailesh Chittipeddi, Charles Walter Pearce, Pradip Kumar Roy
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Patent number: 6387772Abstract: A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.Type: GrantFiled: April 25, 2000Date of Patent: May 14, 2002Assignee: Agere Systems Guardian Corp.Inventors: Sailesh Chittipeddi, Charles Walter Pearce, Pradip Kumar Roy
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Patent number: 6361614Abstract: A method and apparatus for eliminating the exposure of semiconductor wafers to light during rinsing and drying in wafer cleaning machines having windows is used to reduce scrap and improve the reliability of the integrated circuit devices. An opaque window assembly or a light blocking material is applied to the transparent window to prevent ambient light from entering the processing chamber of the wafer cleaning machine and thereby eliminate light-induced galvanic corrosion produced during rinsing and drying of semiconductor wafers in wafer cleaning machines having windows. This makes the fabrication of advanced integrated circuit devices of increasingly smaller dimensions feasible by eliminating the degradation in reliability caused by light-induced galvanic corrosion produced during cleaning of the semiconductor wafers. The application of a light blocking material to the transparent windows of wafer cleaning machine is cost effective and easily implemented in existing wafer cleaning machines.Type: GrantFiled: February 22, 2000Date of Patent: March 26, 2002Assignee: Agere Systems Guardian Corp.Inventors: Bryan Chaeyoo Chung, Glenn Alan Marshall, Charles Walter Pearce, Kevin Paul Yanders
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Patent number: 6358865Abstract: A method is disclosed for the oxidation of a substrate and the formation of oxide regions in the substrate by implantation of fluorine into the silicon lattice and subsequently forming an oxide region by a typical oxide growth process. The oxide growth process may be those such as thermal oxidation or the local oxidation of silicon. The process according to the present invention allows for the simultaneous growth of oxides having different thicknesses at the same time by tailoring the fluorine implantation.Type: GrantFiled: May 14, 1999Date of Patent: March 19, 2002Assignee: Agere Systems Guardian Corp.Inventors: Charles Walter Pearce, Daniel Joseph McKee, Jeffrey Kenneth Haas
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Publication number: 20020001972Abstract: A method is disclosed for the oxidation of a substrate and the formation of oxide regions in the substrate by implantation of fluorine into the silicon lattice and subsequently forming an oxide region by a typical oxide growth process. The oxide growth process may be those such as thermal oxidation or the local oxidation of silicon. The process according to the present invention allows for the simultaneous growth of oxides having different thicknesses at the same time by tailoring the fluorine implantation.Type: ApplicationFiled: May 14, 1999Publication date: January 3, 2002Inventors: CHARLES WALTER PEARCE, DANIEL JOSEPH MCKEE, JEFFREY KENNETH HAAS
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Publication number: 20010029068Abstract: An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer.Type: ApplicationFiled: June 11, 2001Publication date: October 11, 2001Inventors: Sailesh Chittipeddi, Charles Walter Pearce
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Patent number: 6294807Abstract: An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent difflusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer.Type: GrantFiled: February 26, 1999Date of Patent: September 25, 2001Assignee: Agere Systems Guardian Corp.Inventors: Sailesh Chittipeddi, Charles Walter Pearce
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Patent number: 6245692Abstract: A method for manufacturing integrated circuits; particularly, a method to alter heat flow on a localized basis, when heating wafers to elevated temperatures, to achieve different processing temperatures by altering the material properties, such as emissivity, absorptivity and reflectivity, of a portion of a surface by the application of thin films of various materials.Type: GrantFiled: November 23, 1999Date of Patent: June 12, 2001Assignee: Agere Systems Guardian Corp.Inventors: Charles Walter Pearce, Michael Steven Billig
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Patent number: 5930650Abstract: Semiconductor integrated circuit processing is facilitated by an etch process illustratively applied to polysilicon and silicon nitride removal. The etch process illustratively comprises of the use of phosphoric acid with metal-containing additives to bring about an enhanced silicon etch rate effect.Type: GrantFiled: August 1, 1997Date of Patent: July 27, 1999Inventors: Bryan Chaeyoo Chung, Charles Walter Pearce