Abstract: A bidirectional electroosmotic pump may be provided. The bidirectional electroosmotic pump may be made of materials that are biocompatible and non-ferrous. The bidirectional electroosmotic pump may be part of an implantable medical device for the purpose of medicine delivery. The bidirectional electroosmotic pump may contain a working fluid and may facilitate the delivery of a separate payload fluid. In an exemplary embodiment, the bidirectional pump may contain bellows which may allow the pump to deliver the payload fluid through a series of valves and/or catheters. In another embodiment the bidirectional electroosmotic pump may contain a pump sensing mechanism to monitor the state of the pump.

Abstract: A bidirectional electroosmotic pump may be provided. The bidirectional electroosmotic pump may be made of materials that are biocompatible and non-ferrous. The bidirectional electroosmotic pump may be part of an implantable medical device for the purpose of medicine delivery. The bidirectional electroosmotic pump may contain a working fluid and may facilitate the delivery of a separate payload fluid. In an exemplary embodiment, the bidirectional pump may contain bellows which may allow the pump to deliver the payload fluid through a series of valves and/or catheters. In another embodiment the bidirectional electroosmotic pump may contain a pump sensing mechanism to monitor the state of the pump.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from the back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.

Abstract: Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an integrated circuit includes providing an integrated circuit comprising an inner lead bondpad. A first insulative passivation layer is formed over the integrated circuit. A bondpad-redistribution line is formed over the first insulative passivation layer and in electrical connection with the inner lead bondpad through the first insulative passivation layer. The bondpad-redistribution line includes an outer lead bondpad area. A second insulative passivation layer is formed over the integrated circuit and the bondpad-redistribution line. The second insulative passivation layer is formed to have a sidewall outline at least a portion of which is proximate to and conforms to at least a portion of the bondpad-redistribution line. Other aspects and implementations are contemplated.

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

Abstract: A hand-held conduit-cutting device is disclosed. The device uses a battery powered, motor driven reciprocating saw blade to cut electrical conduit and other tubing. The apparatus can be angled to a variety of positions to make positioning the conduit-cutting device easier for cutting the conduit or other tubing.

Abstract: Methods and apparatuses for releasably attaching microfeature workpieces to support members are disclosed herein. In one embodiment, a method includes applying a first material to a first region on a first side of a microfeature workpiece. The method then includes releasably attaching the first side of the workpiece to a support member. The method further includes applying a second material to a second region on the first side of the workpiece. The second region includes a perimeter portion of the workpiece. The first material and/or the second material can be an adhesive. The second material is removable from the workpiece relative to the first material. In several embodiments, for example, the first material can have a first solubility in a solution and the second material can have a second solubility in the solution less than the first solubility.

Abstract: A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon, may be provided and a dielectric layer may be formed thereover. At least one depression may be laser ablated in the dielectric layer and an electrically conductive material may be deposited thereinto. Also, a method for assembling a semiconductor die having a plurality of bond pads and a dielectric layer formed thereover to a carrier substrate having a plurality of terminal pads is disclosed. At least one depression may be laser ablated into the dielectric layer and a conductive material may be deposited thereinto for electrical communication between the semiconductor die and the carrier substrate. The semiconductor die may be affixed to the carrier substrate and at least one of the dielectric layer and the conductive material may remain substantially solid during affixation therebetween. The methods may be implemented at the wafer level.

Abstract: A method for fabricating a semiconductor component includes the steps of providing a semiconductor die, forming a plurality of redistribution contacts on the die, forming a plurality of interconnect contacts on the redistribution contacts, and forming an insulating layer on the interconnect contacts while leaving the tip portions exposed. The method also includes the step of forming terminal contacts on the interconnect contacts, or alternately forming conductors in electrical communication with the interconnect contacts and then forming terminal contacts in electrical communication with the conductors.

Abstract: Microfeature workpieces, carriers, and associated methods are disclosed. In a particular embodiment, one method for processing a microfeature workpiece can include temporarily attaching the microfeature workpiece to a carrier with a releasable connector, wherein the connector is at least partially metallic. The method can further include performing a manufacturing process on the microfeature workpiece while the microfeature workpiece is attached to the carrier. The method can still further include detaching the microfeature workpiece from the carrier by debonding the connector from at least one of the microfeature workpiece and the carrier. In at least some instances, the at least partially metallic connector can withstand increased processing temperatures, and can allow a wider variety of processes to be performed on the microfeature workpiece while it is attached to the carrier.

Abstract: An apparatus for placing lines in a conduit is disclosed. The device uses a battery powered, motor driven wheeled body to roll through the conduit pulling a jet line. The apparatus is used instead of “fish” tape, vacuum, or compressed air to draw a jet line through the conduit.

Abstract: An apparatus for placing lines in a conduit is disclosed. The apparatus uses a battery powered electric fan in an aerodynamically shaped body to fly through the conduit pulling a jet line. The apparatus is used instead of “fish” tape, vacuum, or compressed air to draw a jet line through the conduit.

Abstract: Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the bond-pad being electrically coupled to the integrated circuit. A conductive line is then formed on the die, the conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line, and depositing an electrically conductive material in at least a portion of the passage to form a conductive interconnect extending at least generally through the microelectronic device.

Abstract: Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.