Abstract: A core voltage for a core logic region of an integrated circuit is specified by a programmable register on the integrated circuit. Output terminals on the integrated circuit are coupled to the programmable storage location and supply voltage control signals for a voltage regulator to specify the core voltage according to the contents of the programmable register. The output terminals may output a programmable voltage setting or a fixed voltage setting that specifies a default core voltage value, depending on reset conditions.

Abstract: A processor includes an input/output (I/O) register that is mapped into input/output (I/O) address space. The processor also includes a base address register that is loaded with a base address. The base address register may be a model specific register (MSR). The input/output register is accessed with an input/output instruction at an address determined according to the base address and an offset therefrom. The base address register may be accessible to software operating at a high privilege level and not accessible to software operating at a lower privilege level, while the I/O register is accessible to software operating at the lower privilege level. The processor determines when an I/O access is to the processor I/O register and accesses that I/O register without causing an input/output bus cycle that would otherwise occur.