Abstract: A mask structure and photolithographic method using the same for obtaining shorter and thinner line or feature lengths for optimizing power consumption and performance in semiconductor devices. According to a first aspect, a method for enabling trimming of semiconductor linewidth dimensions implements an extra dose trim mask. The lithographic method using the extra dose trim mask to make small adjustments to patterned linewidth exposures for enhanced CD control may be used to trim or adjust whole or a plurality of regions of a lithographic exposure. There is additionally provided a structure and method of creating a lithographic dual exposure mask having one or more regions comprising one or more partial energy absorptive layers such that, when subject to a blanket dose, enable smaller image size adjustments in those regions.

Abstract: The present invention relates to determining the location of a defect source which results in a localized elevation on the surface topography of a substrate such as, for example, a silicon wafer. The wafer is placed on a chuck of a semiconductor process tool such as, for example, a photolithographic tool. The upper surface of the wafer is processed by the photolithographic tool to obtain topography measurements. The topography measurements are analyzed to detect the presence of the localized elevation on the upper surface of the wafer. Once the presence of the localized elevation is detected, calculations are performed using the topography measurements to determine whether the source of the localized elevation results from the chuck.