Abstract: A manufacturing execution system may be simulated, for example, for volume testing. In a semiconductor fabrication embodiment, a volume capability, such as a number of wafer starts, may be determined for a given version of a manufacturing execution system. In some cases, the simulation runs operations or scripts under more realistic conditions. A check can determine whether an appropriate condition exists at an appropriate lot or tool and the desired operation may then be run from that lot or tool from an appropriate state.

Abstract: According to embodiments of the invention, an integrated configuration, flow and execution systems (ICFES) may be used to specify, control and record a history of processing of both semiconductor device experimental lots and production lots of wafers. Moreover, the system allows combining of one or more partial flows of pre-existing flow blocks, and special processing into another processing flow block. A lot plan can be created that includes the flow block, and the lot plan can be updated to include partial flows and special processing before or during processing of the lot plan.

Abstract: In one embodiment, a method for upfront specification of lot process parameters to enable automated processing is disclosed. The method comprises building a hierarchical representation of a process plan for a manufacturing object using data structures to represent operational flows of the manufacturing object, performing a query execution on the hierarchical representation to determine one or more of the data structures affected by a global flow change (GFC), and implementing a locking protocol to preserve data integrity in the one or more data structures affected by the GFC. Other embodiments are also described.

Abstract: A system for conducting transistor performance analysis is disclosed, in which automatic graph plotting is interactively enhanced with human judgment. The system includes executing transistor performance analysis software, which receives templates specifying parameters, graph charting options, and algorithms, as well as a database of transistor values, as its inputs. The software produces an output document with linked graphs and a summary report. The software extracts, filters and applies statistical regression to large quantities of data. The software also applies statistical filtering to the data and automatically plots hundreds of charts and graphs based on the data. Graphs are color-coded to highlight relationships that suffer from unusually high noise in the data. Users can manually adjust lines on the graphs, which are automatically reflected in dependent graphs and the summary report. Changes to program methodology can be achieved by changing the template rather than by modifying the software.

Abstract: Automating techniques provide a way to create efficient test programs for characterizing semiconductor devices, such as those on a silicon die sample. Typically, test program creation is a drawn out process involving data entry for every test to be run as part of the test program. The described techniques improve test algorithm selection and automatically populate the test algorithm data in creating the test program. The automatic population may occur by accessing test structure, header, and test algorithm catalogs. The test structure catalog contains physical data for the test program, while the header catalog contains global parameter values. The test algorithm catalog has all of the various test algorithms that may be run in a given test, where these test algorithms may be in a template form and specific to any number of different test language abstractions. After test program creation, a validation process is executed to determine if the test program data is valid.