Patents by Inventor Charlie C. Hwang
Charlie C. Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8295419Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.Type: GrantFiled: October 18, 2010Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: Charlie C. Hwang, Wiren D. Becker, Timothy G. McNamara, Ching-Lung Tong
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Patent number: 8291157Abstract: Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of the cache memory, transmitting a starting time of the refresh time interval to a bank controller, the bank controller being local to, and associated with, only one cache memory bank of the cache memory, sampling a continuous refresh status indicative of a number of refreshes necessary to maintain data within the cache memory bank associated with the bank controller, requesting a gap in a processing pipeline of the cache memory to facilitate the number of refreshes necessary, receiving a refresh grant in response to the requesting, and transmitting an encoded refresh command to the bank controller, the encoded refresh command indicating a number of refresh operations granted to the cache memory bank associated with the bank controller.Type: GrantFiled: June 24, 2010Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Timothy C. Bronson, Hieu T. Huynh, Charlie C. Hwang, Kenneth D. Klapproth
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Patent number: 8258758Abstract: A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage.Type: GrantFiled: July 1, 2008Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventors: Charlie C. Hwang, Paul D. Muench, Donald W. Plass, Michael Sperling
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Publication number: 20110320700Abstract: Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of the cache memory, transmitting a starting time of the refresh time interval to a bank controller, the bank controller being local to, and associated with, only one cache memory bank of the cache memory, sampling a continuous refresh status indicative of a number of refreshes necessary to maintain data within the cache memory bank associated with the bank controller, requesting a gap in a processing pipeline of the cache memory to facilitate the number of refreshes necessary, receiving a refresh grant in response to the requesting, and transmitting an encoded refresh command to the bank controller, the encoded refresh command indicating a number of refresh operations granted to the cache memory bank associated with the bank controller.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Bronson, Hieu T. Huynh, Charlie C. Hwang, Kenneth D. Klapproth
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Publication number: 20110033017Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.Type: ApplicationFiled: October 18, 2010Publication date: February 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charlie C. Hwang, Wiren D. Becker, Timothy G. McNamara, Ching-Lung Tong
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Patent number: 7831946Abstract: A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid.Type: GrantFiled: July 31, 2007Date of Patent: November 9, 2010Assignee: International Business Machines CorporationInventors: Rick L. Dennis, Charlie C. Hwang, Jose L. Neves
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Patent number: 7826579Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.Type: GrantFiled: February 28, 2006Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Charlie C. Hwang, Wiren D. Becker, Timothy G. McNamara, Ching-Lung Tong
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Patent number: 7659740Abstract: Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal.Type: GrantFiled: August 11, 2008Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Joseph O. Marsh, Jeremy Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu, Matthew B. Baecher, Thomas J. Bardsley, Mark R. Taylor
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Publication number: 20100001709Abstract: A system to generate a reference for a charge pump may include a diode-connected transistor providing a reference voltage, and an output transistor. The system may also include a reference circuit to provide a current that is substantially temperature insensitive and the reference circuit delivers the current across the diode-connected transistor thereby enabling the reference voltage to move with processing of the diode-connected transistor.Type: ApplicationFiled: July 6, 2008Publication date: January 7, 2010Inventors: John E. Barth, JR., Charlie C. Hwang, Paul D. Muench, Donald W. Plass, Michael Sperling
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Publication number: 20100001696Abstract: A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage.Type: ApplicationFiled: July 1, 2008Publication date: January 7, 2010Inventors: Charlie C. Hwang, Paul D. Muench, Donald W. Plass, Michael Sperling
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Publication number: 20100002478Abstract: A system to improve a voltage multiplier may include a voltage multiplier circuit, and a capacitor carried by the multiplier circuit. The system may also include a transistor to charge an up voltage of the capacitor.Type: ApplicationFiled: July 2, 2008Publication date: January 7, 2010Inventors: Charlie C. Hwang, Paul D. Muench, Donald W. Plass, Michael Sperling
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Publication number: 20090033398Abstract: A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rick L. Dennis, Charlie C. Hwang, Jose L. Neves
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Publication number: 20090027075Abstract: A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.Type: ApplicationFiled: August 11, 2008Publication date: January 29, 2009Applicant: International Business Machines CorporationInventors: Joseph O. Marsh, Jeremy Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu, Matthew B. Baecher, Thomas J. Bardsley, Mark R. Taylor
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Patent number: 7466156Abstract: A circuit of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention includes a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.Type: GrantFiled: March 25, 2004Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Joseph O. Marsh, Jeremy Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu, Matthew B. Baecher, Thomas J. Bardsley, Mark R. Taylor
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Patent number: 7456671Abstract: A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applications. The modular design allows the circuit and its layout to be synthesized by software to achieve desired delay resolution and range. Constant capacitive load of internal node enhances the linearity of achieved delay by digital controls.Type: GrantFiled: January 11, 2007Date of Patent: November 25, 2008Assignee: International Business Machines CorporationInventors: Charlie C. Hwang, Phillip J. Restle, Leon J. Sigal
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Publication number: 20080191753Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.Type: ApplicationFiled: April 21, 2008Publication date: August 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINE CORPORATIONInventors: William V. Huott, Charlie C. Hwang, Timothy G. McNamara
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Publication number: 20080169857Abstract: A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applications. The modular design allows the circuit and its layout to be synthesized by software to achieve desired delay resolution and range. Constant capacitive load of internal node enhances the linearity of achieved delay by digital controls.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charlie C Hwang, Phillip J. Restle, Leon J. Sigal
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Patent number: 7382844Abstract: A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the “time zero” of the chips.Type: GrantFiled: February 11, 2005Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Charlie C. Hwang, Timothy G. McNamara, Ching-Lung Tong, Wiren Dale Becker
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Patent number: 7368958Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.Type: GrantFiled: May 19, 2006Date of Patent: May 6, 2008Assignee: International Business Machines CorporationInventors: William V. Huott, Charlie C. Hwang, Timothy G. McNamara
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Patent number: 7355460Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.Type: GrantFiled: January 27, 2006Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: William V. Huott, Charlie C. Hwang, Timothy G. McNamara