Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.

Abstract: Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. A first voltage is applied across a first group of memory cells for the operation and a lower second voltage is applied across other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells and repeated until the operations covers all the groups.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Abstract: Single thyristor memory cells form a volatile memory array. A sense amplifier reads the state of the thyristor in a selected memory cell against a dummy cell through precharged lines.

Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled for an operation on a set of memory cells in an array, sequentially engaging subsets of memory cells for the operation while keeping the remaining memory cells of the set on hold until all the memory cells of the set have been operated on.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: Apparatus and methods for reducing minority carriers in a memory array are described herein. Minority carriers diffuse between ON cells and OFF cells, causing disturbances during write operation as well as reducing the retention lifetime of the cells. Minority Carrier Lifetime Killer (MCLK) region architectures are described for vertical thyristor memory arrays with insulation trenches. These MCLK regions encourage recombination of minority carriers. In particular, MCLK regions formed by conductors embedded along the cathode line of a thyristor array, as well as dopant MCLK regions are described, as well as methods for manufacturing thyristor memory cells with MCLK regions.

Abstract: Thyristor memory cell arrays and their fabrication have improved features. Assist-gates between thyristor memory cells in an array operate on both sides of an assist-gate. The assist-gates can be arranged in various ways for optimized performance and the materials of the assist-gate are selected to control the bias voltage of the assist-gate in operation. The PNPN (or NPNP) thyristor layers of the memory cell can be fabricated in different process flows according to manufacturing concerns and the dopant concentrations of the layers are selected to reduce temperature sensitivity of the memory cell.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

Abstract: Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. An operation is performed on at least one memory cell in a first group of memory cells out of a plurality of groups of memory cells coupled to a line. A first voltage is applied across the first group of memory cells for the operation and a lower second voltage is applied across the other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells. These steps may repeated until the operations covers all the groups.

Abstract: A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

Abstract: Single thyristor memory cells form a volatile memory array. A sense amplifier reads the state of the thyristor in a selected memory cell against a dummy cell through precharged lines.

Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.

Abstract: A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.

Abstract: An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming MOSFET. The balanced layout of the memory cell improves photolithographic effects with a resulting improved process results. Results of programming the memory cell is also improved.