Abstract: Embodiments relate generally to systems and methods for absorbing moisture within a face mask worn by a user. A face mask may comprise at least one layer of filtration material. configured to filter one or more harmful substances from the air breathed by a user; at least one layer of absorbent material configured to absorb moisture exhaled by the user, wherein the at least one layer of absorbent material spans the entire inner surface area of the mask; at least one layer of waterproof material located between the at least one layer of filtration material and the at least one layer of absorbent material configured to prevent moisture from the absorbent material from contacting the filtration material; and at least one layer of anti-bacterial material located adjacent to the at least one layer of absorbent material and forming the inner surface of the mask.

Abstract: A face mask (100) may comprise at least one layer of filtration material (218) configured to filter one or more harmful substances from the air breathed by a user; at least one layer of absorbent material (214) configured to absorb moisture exhaled by the user, wherein the at least one layer of absorbent material (214) spans the entire inner surface area of the mask (100); at least one layer of waterproof material (216) located between the at least one layer of filtration material (218) and the at least one layer of absorbent material (214) configured to prevent moisture from the absorbent material from contacting the filtration material; and at least one layer of anti-bacterial material (212) located adjacent to the at least one layer of absorbent material (214) and forming the inner surface of the mask (100). The face mask (100) can absorb moisture exhaled by a user.

Abstract: A face mask (100) may comprise at least one layer of filtration material (218) configured to filter one or more harmful substances from the air breathed by a user; at least one layer of absorbent material (214) configured to absorb moisture exhaled by the user, wherein the at least one layer of absorbent material (214) spans the entire inner surface area of the mask (100); at least one layer of waterproof material (216) located between the at least one layer of filtration material (218) and the at least one layer of absorbent material (214) configured to prevent moisture from the absorbent material from contacting the filtration material; and at least one layer of anti-bacterial material (212) located adjacent to the at least one layer of absorbent material (214) and forming the inner surface of the mask (100). The face mask (100) can absorb moisture exhaled by a user.

Abstract: A handheld puzzle is described. The puzzle reduces friction between moveable pieces and at the same time allows for restrained alignment of the moveable pieces. An inner core of the puzzle can be adapted for use with a plurality of outer moveable face pieces that can comprise a variety of surface geometries.

Abstract: Engine coolant and its related components is a vital fluid in any internal combustion engine, however it is one of the most neglected systems in the vehicle. The newest domestic automobiles do not have service indicators for engine coolant; which would allow the owner to service the fluid before any serious damage occurs from electrolysis and metal breakdown. The proposed Coolant Service Monitoring System (CSMS) will utilize sensors to monitor the pH of the coolant mixture, as well as the DC voltage of the coolant with respect to ground. By monitoring the pH and voltage, the sensors can notify the operator when unsafe coolant conditions are present. Ultimately, by preventing excessive corrosion and accelerated electrolysis, automobile owners can save hundreds if not thousands of dollars by not having to replace heater cores, expensive radiators, and water pumps with the CSMS implemented in the vehicle.

Abstract: This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and takes advantage of the length between the heat sink and the first mold packaged materials at the first axis to be about equal to the length between the chip and the second mold packaged materials at the first axis to prevent producing voids that would form unbalanceable thermal mold flow. The heat sink can also dissipate heat from the lead frame to others spaces in the integrated circuit packages. This method and means can prevent delaminating and cracking occurring in the chip and can increase the quality of integrated circuits.

Abstract: A method for determining failure rate and selecting a best burn-in time is disclosed. The method comprises the following steps. First of all, integrate circuits are provided. Then a life-time testing process is performed, wherein a failure rate versus testing time relation is established by measuring the life-time of each integrated circuit under a testing environment, wherein an acceleration factor function also is established under the testing environment. Next a simulating process that uses a testing time function is performed to simulate the failure rate versus testing time relation. Then a transforming process that uses the acceleration factor function is performed to transform the testing time function into a real time function. Finally, an integrating process is performed to integrate the real time function through a calculating region to acquire an accumulated failure rate real time function.

Abstract: A memory controller and associated memory device having a universal serial bus (USB) interface thereon. The memory controller receives a USB instruction via the USB interface. After decoding the USB instruction, the memory controller controls the flow of data to and from a coupled memory unit. The memory unit may contain read-only-memory, one time programmable memory or static random access memory by selection.

Abstract: A backplane with multiple arrayed electrodes positioned on the backplane is provided in a method of fabricating a liquid crystal (LC) panel. The method begins with coating an alignment layer on the backplane. By performing a rubbing process, multiple alignment trenches are formed on the alignment layer. A photoresist layer is then formed on the alignment layer. By performing a lithography process, both a side frame, having at least one slit, and multiple photoresist spacers(PR spacers) are formed on the alignment layer. A gasket seal is coated on the side frame and the multiple PR spacers. By performing a lamination process, a transparent conductive layer is laminated on the backplane. A liquid crystal filling (LC filling) processis then performed to fill a cell gap between the backplane and the transparent conductive layer with liquid crystal. Finally, an end sealing process is performed to seal the slit.

Abstract: A flash memory bridging device, method and application system. The flash memory bridging device provides a buffer region that serves as a cache for storing the address of a portion of a NAND flash memory. A cache control logic inside the flash memory bridging device is used to determine if the requested data is a cache hit so that a direct response is possible or a cache miss so that waiting is demanded. During a data read operation, an error correction function is implemented so that data errors are corrected. Using NAND flash memory to simulate the operation of the NOR flash memory and store program code and data not only lowers production cost, but also improves overall performance and reliability of the system.

Abstract: This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and take advantage of the length between the heat sink and the first mold packaged materials at the first axis to be about equal to the length between the chip and the second mold packaged materials at the first axis to prevent producing voids form unbalanceable thermal mold flow. The heat sink can also dissipating heat from the lead frame to others spaces in the integrated circuit packages. This method and means can prevent delaminating and cracking occurring in the chip and increasing the qualities in integrated circuits.

Abstract: A backplane with multiple arrayed electrodes positioned on the backplane is provided in a method of fabricating a liquid crystal (LC) panel. The method begins with coating an alignment layer on the backplane. By performing a rubbing process, multiple alignment trenches are formed on the alignment layer.A photoresist layer is then formed on the alignment layer. By performing a lithography process, both a side frame, having at least one slit, and multiple photoresist spacers(PR spacers) are formed on the alignment layer. A gasket seal is coated on the side frame and the multiple PR spacers. By performing a lamination process, a transparent conductive layer is laminated on the backplane. A liquid crystal filling (LC filling) process is then performed to fill a cell gap between the backplane and the transparent conductive layer with liquid crystal. Finally, an end sealing process is performed to seal the slit.

Abstract: A silicon backpanel structure of a LCOS is described. The present silicon back panel has a cell region and a routing/pad region, wherein the cell region of the silicon backpanel is arranged with a plurality of pixels and an alignment layer is disposed over the silicon backpanel, and the routing/pad region is arranged with a patterned trace and a plurality of routing/pads, and the routings/pads are electrically bonded to the pixels by means of the patterned trace. Furthermore, the patterned trace of the routing/pad regions is mounted with a break protective layer. This break protective layer protects the patterned trace of the routing/pad region from damage by the pressing of the upper transparent substrate in the subsequent breaking stage.

Abstract: An architecture for wafer scale memories and a placement method replaces defective chips with spare chips in a memory module so as to provide minimum critical signal delay. The SDRAM memory chips are classified into normal chips and spare chips, where the normal chips are formed into groups such as rows or columns, and the spare chips are used to replace defective normal chips. A delay model for metal lines and vias is used to compute the signal delay for placement and routing. The placement problem is modeled as a bipartite graph and solved using a branch and bound algorithm to obtain a chip replacement configuration having the shortest critical signal delay. Also described is a hierarchical routing approach, which classifies the signals into different types and levels of signals.

Abstract: A method of fabricating a direct contact through hole type wafer. Devices and contact plugs are formed in one side of a silicon-on-insulator substrate, and multilevel interconnects are formed over the side of the silicon-on-insulator substrate. The multilevel interconnects are coupled with the devices and the contact plugs. Bonding pads, which couples with the multilevel interconnects, are formed over the multilevel interconnects. An opening is formed on the other side of the silicon-on-insulator substrate to expose the contact plugs. An insulation layer, a barrier layer and a metal layer are formed in sequence in the opening. Bumps are formed on the bonding pads and the metal layer, respectively.

Abstract: This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and take advantage of the length between the heat sink and the first mold packaged materials at the first axis to be about equal to the length between the chip and the second mold packaged materials at the first axis to prevent producing voids form unbalanceable thermal mold flow. The heat sink can also dissipating heat from the lead frame to others spaces in the integrated circuit packages. This method and means can prevent delaminating and cracking occurring in the chip and increasing the qualities in integrated circuits.

Abstract: A pad design. The pad design provides an additional testing pad that is electrically connected to a conventional bonding pad and positioned beside the bonding pad. The conventional bonding pad is formed on a provided chip, and a bump is formed on the bonding pad. A final test is performed on the testing pad so that damage formed on the bump or on the bonding pad can be prevented.

Abstract: This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and take advantage of the length between the heat sink and the first mold packaged materials at the first axis to be about equal to the length between the chip and the second mold packaged materials at the first axis to prevent producing voids form unbalanceable thermal mold flow. The heat sink can also dissipating heat from the lead frame to others spaces in the integrated circuit packages. This method and means can prevent delaminating and cracking occurring in the chip and increasing the qualities in integrated circuits.

Abstract: Method for determining failure rate and selecting a best burn-in time, comprising: provide numerous integrate circuits; performs a life-time testing process, wherein a failure rate testing time relation is established by measuring the life-time of each integrated circuit under a testing environment, wherein an acceleration factor function also is established under the testing environment, the acceleration factor function is related to the relationship between a testing time of the testing environment and a real time of a normal operating environment; performs a simulating process that a testing time function is used to simulate the failure rate testing time relation; performs a transforming process by using the acceleration factor function to transform the testing time function into a real time function, wherein a knee point of the real time function corresponds to an operation time which is the best burn-in time; and performs an integrating process to integrate the real time function through a calculating re

Abstract: A dual-dies packaging structure is provided. The dual-dies packaging structure includes a lead frame, which further includes a die pad and several lead legs, in which the die pad includes an upper surface and a lower surface. A first die, having several first bonding pads, is fixed on the upper surface of the die pad by, for example, gluing it. The first bonding pads remain exposed. A second die, having several second bonding pads, is fixed on the lower surface by, for example, gluing it. The second bonding pads remain exposed. A bumping redistribution structure layer is located on the second die so as to redistribute each of the second bonding pads to a pseudo-bonding pad. Each pseudo-bonding pad has its proper location with respect to the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other.