Abstract: Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.

Abstract: Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal. A local pass gate receives the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal.

Abstract: A clock distribution network for distributing a repetitive timing signal throughout an integrated circuit, the timing signal being within a range of frequencies about a first frequency, includes multiple buffer circuits and at least one conductive segment connecting one of the buffers to another of the buffers. The conductive segment has a length selected so as to be less than a quarter-wave resonance length of the conductive segment at the first frequency to thereby achieve duty cycle correction.

Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to?1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the “time zero” of the chips.

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.

Abstract: Circuit designs and methods are provided for matching device characteristics for, e.g., analog or mixed-signal semiconductor integrated circuit designs. In particular, circuit layout patterns and layout methods are provided which enable precise or proportional matching of circuit components by uniformly distributing circuit components in a manner that eliminates or significantly minimizes the sensitivity of such circuit components to environmental effects and process variations, thereby improving the performance of analog and mixed-signal circuits.