Abstract: Multiple network switches are configured having memory interfaces that transfer segmented frame data to each other via a data path having multiple rings connecting the network switches. The memory interfaces are also configured for transferring the segmented frame data to respective local buffer memories for temporary storage. The data path transfers the data units between the switches according to a prescribed sequence protocol, optimizing memory bandwidth by requiring only one read and one write operation to and from a local buffer memory for each segmented frame data being received and transmitted through the switches.

Abstract: Multiple network switches are configured having memory interfaces that transfer segmented packet data to each other via a unidirectional data bus ring connecting the network switches in a single ring or “daisy chain” arrangement. The memory interfaces are also configured for transferring the segmented packet data to respective local buffer memories for temporary storage. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by requiring only one read and one write operation to and from the local buffer memory for each segmented packet data being received and transmitted through the switches.

Abstract: Multiple network switch modules have memory interfaces configured for transferring packet data to respective local buffer memories via local memory controllers. The local memory controllers are connected to each other to form a signal memory pool for transfer among each other data units of data frames received from different network switch modules. Each of the controllers are also connected to a corresponding local buffer memory and either write received data units in the corresponding local buffer memory or transfer the received data units to other controllers that, in turn, write the data units in their corresponding local buffer memory. The local memory controllers transfer and write and read the data units according to a prescribed sequence, optimizing memory bandwidth by concurrently executing a prescribed number of successive memory writes or memory reads.

Abstract: An apparatus and method for detecting runt data frames received by a network switch includes a plurality of queuing logics, corresponding to the number of ports contained in the network switch. The queuing logics transfer received data frames to a memory area of the network switch. The queuing logics also update the value of a column write pointer that indicates the number of data transfers required to store a prescribed portion of a particular received data frame in the memory area. A rules queue examines the column write pointer and determines if the particular data frame is a runt data frame. A runt indication signal is generated, after the particular data frame has been completely transferred to the memory area, in order to indicate if the particular data frame was a runt data frame.

Abstract: A wake-up system is provided to allow host computer access to a Card Information Structure (CIS) on a PCMCIA card during a SLEEP mode. The CIS is stored in a non-volatile memory accessible to a host computer via a PCMCIA bus and to PCMCIA card logic via a local bus. Arbitration logic is coupled between the PCMCIA and local buses to control access to the memory. Sleep logic prevents a fast clock signal from being supplied to the arbitration logic and the PCMCIA card logic when the PCMCIA card is switched into the SLEEP mode. A CIS read detect circuit decodes a CIS read operation on the PCMCIA bus and asserts the CIS detect signal supplied to the sleep logic. In response, the sleep logic allows the fast clock signals to be supplied to the arbitration logic and adapter card subsystem to exit from the SLEEP mode and provide the host computer with access to the memory storing the CIS information.