Patents by Inventor Charlotte Jonas

Charlotte Jonas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240410902
    Abstract: Reliable non-invasive biomarkers are an unmet clinical need for the diagnosis of NASH patients. Herein we identify soluble TREM2 as a non-invasive plasma biomarker to diagnose NASH in obese patients and provides evidence for sTREM2 as an accurate predictor of advanced hepatic inflammation, ballooning, and fibrosis.
    Type: Application
    Filed: May 20, 2022
    Publication date: December 12, 2024
    Inventors: Niels Jonas Heilskov GRAVERSEN, Vineesh Indira CHANDRAN, Søren Kragh MOESTRUP, Maria Kløjgaard SKYTTHE, Aleksander Ahm KRAG, Charlotte WERNBERG, Mette Enok Munk LAURIDSEN
  • Patent number: 9640609
    Abstract: Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: May 2, 2017
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Charlotte Jonas, Anant K. Agarwal
  • Patent number: 9548374
    Abstract: A method of forming a transistor device include forming a drift layer of a first conductivity type, forming a well of a second conductivity type in the drift layer, forming a JFET region with first conductivity type dopant ions in the drift layer, forming a channel adjustment layer of the first conductivity type on the JFET region and the well, implanting first conductivity type dopant ions to form an emitter region of the first conductivity type extending through the channel adjustment layer and into the well, wherein the emitter region is spaced apart from the JFET region by the well, implanting second conductivity type dopant ions to form a connector region of the second conductivity type adjacent the emitter region, forming a gate oxide layer on the channel region, and forming a gate on the gate oxide layer.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: January 17, 2017
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Sei-Hyung Ryu, Charlotte Jonas, Anant K. Agarwal
  • Patent number: 9184237
    Abstract: A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: November 10, 2015
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Craig Capell, Charlotte Jonas, David Grider
  • Publication number: 20150287805
    Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 8, 2015
    Applicant: Cree, Inc.
    Inventors: Qingchun Zhang, Sei-Hyung Ryu, Charlotte Jonas, Anant K. Agarwal
  • Patent number: 9142662
    Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: September 22, 2015
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Doyle Craig Capell, Lin Cheng, Sarit Dhar, Charlotte Jonas, Anant Agarwal, John Palmour
  • Patent number: 9064710
    Abstract: A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: June 23, 2015
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant Agarwal, Charlotte Jonas
  • Patent number: 9029945
    Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Doyle Craig Capell, Lin Cheng, Sarit Dhar, Charlotte Jonas, Anant Agarwal, John Palmour
  • Publication number: 20140374773
    Abstract: A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 25, 2014
    Inventors: Sei-Hyung Ryu, Craig Capell, Charlotte Jonas, David Grider
  • Patent number: 8710510
    Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: April 29, 2014
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Sei-Hyung Ryu, Charlotte Jonas, Anant K. Agarwal
  • Publication number: 20120280270
    Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.
    Type: Application
    Filed: May 16, 2011
    Publication date: November 8, 2012
    Inventors: Sei-Hyung Ryu, Doyle Craig Capell, Lin Cheng, Sarit Dhar, Charlotte Jonas, Anant Agarwal, John Palmour
  • Publication number: 20120280252
    Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.
    Type: Application
    Filed: May 6, 2011
    Publication date: November 8, 2012
    Inventors: Sei-Hyung Ryu, Doyle Craig Capell, Lin Cheng, Sarit Dhar, Charlotte Jonas, Anant Agarwal, John Palmour
  • Publication number: 20120235164
    Abstract: A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
    Type: Application
    Filed: May 29, 2012
    Publication date: September 20, 2012
    Applicant: CREE, INC.
    Inventors: Qingchun Zhang, Anant Agarwal, Charlotte Jonas
  • Patent number: 8211770
    Abstract: A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: July 3, 2012
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant Agarwal, Charlotte Jonas
  • Publication number: 20110250737
    Abstract: A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 13, 2011
    Applicant: CREE, INC.
    Inventors: Qingchun Zhang, Anant Agarwal, Charlotte Jonas
  • Patent number: 7989882
    Abstract: A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: August 2, 2011
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant Agarwal, Charlotte Jonas
  • Publication number: 20090146154
    Abstract: A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 11, 2009
    Applicant: Cree, Inc.
    Inventors: Qingchun Zhang, Anant Agarwal, Charlotte Jonas
  • Publication number: 20080105949
    Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.
    Type: Application
    Filed: June 18, 2007
    Publication date: May 8, 2008
    Inventors: Qingchun Zhang, Sei-Hyung Ryu, Charlotte Jonas, Anant K. Agarwal