Patents by Inventor Charudatta Mandhare

Charudatta Mandhare has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BiCMOS integration of multiple-times-programmable non-volatile memories
    Patent number: 7989875
    Abstract: A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the buried carrier layer portion within the DTI trench. A floating gate is disposed on the carrier well. Optionally, a high voltage control gate is formed of a stack of the buried well implant and the surface well implant within the DTI trench. Optionally, a poly layer formed of a bipolar process base poly layer is disposed on the floating gate. Optionally, a shallow well isolation region is formed on the substrate, a floating gate is disposed on the shallow well region, and an overlaying control gate, formed of a bipolar process base poly, is disposed above the floating gate.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: August 2, 2011
    Assignee: NXP B.V.
    Inventors: Wibo Van Noort, Theodore James Letavic, Francis Zaato, Charudatta Mandhare
  • BICMOS INTEGRATION OF MULTIPLE-TIMES-PROGRAMMABLE NON-VOLATILE MEMORIES
    Publication number: 20100127318
    Abstract: A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the buried carrier layer portion within the DTI trench. A floating gate is disposed on the carrier well. Optionally, a high voltage control gate is formed of a stack of the buried well implant and the surface well implant within the DTI trench. Optionally, a poly layer formed of a bipolar process base poly layer is disposed on the floating gate. Optionally, a shallow well isolation region is formed on the substrate, a floating gate is disposed on the shallow well region, and an overlaying control gate, formed of a bipolar process base poly, is disposed above the floating gate.
    Type: Application
    Filed: November 24, 2008
    Publication date: May 27, 2010
    Applicant: NXP B.V.
    Inventors: Wibo Van NOORT, Theodore James Letavic, Francis Zaato, Charudatta Mandhare