Abstract: A computer-implemented method includes receiving a text description of a logic circuit design, reading a plurality of circuit priority indicator values, synthesizing a logic circuit design based, at least in part, on those circuit priority indicator values, and fabricating logic circuits using the synthesized logic circuit design. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A computer-implemented method includes receiving a text description of a logic circuit design, reading a plurality of circuit priority indicator values, synthesizing a logic circuit design based, at least in part, on those circuit priority indicator values, and fabricating logic circuits using the synthesized logic circuit design. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A computer-implemented method includes receiving, with one or more processors, a text-based description of a logic circuit comprising a plurality of logic sub-circuits, determining within the text-based description, with one or more processors, a set of circuit priority indicators for a corresponding set of the logic sub-circuits, and synthesizing, with one or more processors, the logic circuit according to the set of circuit priority indicators to provide a synthesized circuit description. A corresponding computer program product and computer system are also disclosed herein.

Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.

Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.

Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.

Abstract: A computer-implemented method includes receiving, with one or more processors, a text-based description of a logic circuit comprising a plurality of logic sub-circuits, determining within the text-based description, with one or more processors, a set of circuit priority indicators for a corresponding set of the logic sub-circuits, and synthesizing, with one or more processors, the logic circuit according to the set of circuit priority indicators to provide a synthesized circuit description. A corresponding computer program product and computer system are also disclosed herein.

Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.

Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.

Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.

Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.

Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.

Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.

Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.

Abstract: Various embodiments include: determining boundary vertices for an ECO within a placed netlist based on: a first weight assigned to a gate array distribution; and a second weight assigned to routing congestion, the boundary vertices defining a polygon; implementing the ECO at gate level; estimating slack value for determined boundary vertices; assigning vertex weights to boundary vertices based on the estimated slack values for boundary vertices; calculating a weighted centroid location for the polygon, based on the vertex weights; locating spare latches in the placed netlist; determining a clock domain and a clock gating domain for each located spare latch; assigning a cost function to each located spare latch having a same clock domain and a same clock gating domain as the ECO; ranking each respective cost function for each located spare latch; and selecting the desired spare latch based on the ranking of the each located spare latch.

Abstract: A method, software in the form of a computer readable medium, and a system for designing an integrated circuit. The method comprises providing in a library of shapes, a at least one shape used to define regions of the integrated circuit in which no active chip circuits are placed; and utilizing the library to design the integrated circuit. GDS data corresponding to the design of the integrated circuit includes data representing said at least one shape as a dummy element.