Abstract: Embodiments of an electroentropic memory device comprising an array of electroentropic storage devices (EESDs) are disclosed, as well as methods of making and using the electroentropic memory device. The memory device includes a plurality of address lines arranged in rows to select a row of the EESDs and a plurality of data lines arranged in columns to select a column of the EESDs, wherein each EESD is coupled in series between an address line connected to one side of the EESD and a data line connected to an opposing side of the EESD. The memory device may have a stacked architecture with multiple layers of address lines, data lines, and EESDs. The disclosed electroentropic memory devices are operable in ROM and RAM modes. EESDs in the disclosed electroentropic memory devices may include from 2-4096 logic states and/or have a density from 0.001 kb/cm3 to 1024 TB/cm3.

Abstract: Embodiments of an electroentropic memory device comprising an array of electroentropic storage devices (EESDs) are disclosed, as well as methods of making and using the electroentropic memory device. The memory device includes a plurality of address lines arranged in rows to select a row of the EESDs and a plurality of data lines arranged in columns to select a column of the EESDs, wherein each EESD is coupled in series between an address line connected to one side of the EESD and a data line connected to an opposing side of the EESD. The memory device may have a stacked architecture with multiple layers of address lines, data lines, and EESDs. The disclosed electroentropic memory devices are operable in ROM and RAM modes. EESDs in the disclosed electroentropic memory devices may include from 2-4096 logic states and/or have a density from 0.001 kb/cm3 to 1024 TB/cm3.