Patents by Inventor Chau-Jie Zhan
Chau-Jie Zhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9391049Abstract: A molding package assembly is provided, which includes a substrate and first and second molding packages stacked on the substrate. Each of the first and second molding packages has a semiconductor element, an anti-warping structure disposed around a periphery of the semiconductor element, a molding material encapsulating the semiconductor element and the anti-warping structure, and a protection layer formed on the semiconductor element, the molding material and the anti-warping structure. The anti-warping structure facilitates to prevent warping of the molding package assembly during a molding process.Type: GrantFiled: December 5, 2014Date of Patent: July 12, 2016Assignee: Industrial Technology Research InstituteInventors: Yu-Min Lin, Chau-Jie Zhan
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Publication number: 20150187737Abstract: A molding package assembly is provided, which includes a substrate and first and second molding packages stacked on the substrate. Each of the first and second molding packages has a semiconductor element, an anti-warping structure disposed around a periphery of the semiconductor element, a molding material encapsulating the semiconductor element and the anti-warping structure, and a protection layer formed on the semiconductor element, the molding material and the anti-warping structure. The anti-warping structure facilitates to prevent warping of the molding package assembly during a molding process.Type: ApplicationFiled: December 5, 2014Publication date: July 2, 2015Applicant: Industrial Technology Research InstituteInventors: Yu-Min Lin, Chau-Jie Zhan
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Patent number: 9024441Abstract: A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.Type: GrantFiled: May 31, 2012Date of Patent: May 5, 2015Assignee: Industrial Technology Research InstituteInventors: Yu-Min Lin, Chau-Jie Zhan, Tao-Chih Chang
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Patent number: 8598686Abstract: The invention provides an electronic device package structure and method of fabrication thereof. The electronic device package structure includes a chip having an active surface and a bottom surface. A dielectric layer is disposed on the active surface of the chip. At least one trench is formed through the dielectric layer. A first protection layer covers the dielectric layer and sidewalls of the trench. A second protection layer covers the first protection layer, filling the trench.Type: GrantFiled: September 27, 2010Date of Patent: December 3, 2013Assignee: Industrial Technology Research InstituteInventors: Tao-Chih Chang, Su-Tsai Lu, Jing-Yao Chang, Chau-Jie Zhan
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Patent number: 8575754Abstract: A dished micro-bump structure with self-aligning functions is provided. The micro-bump structure takes advantage of the central concavity for achieving the accurate alignment with the corresponding micro-bumps.Type: GrantFiled: September 17, 2010Date of Patent: November 5, 2013Assignee: Industrial Technology Research InstituteInventors: Tsung-Fu Tsai, Tao-Chih Chang, Chau-Jie Zhan
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Publication number: 20130168851Abstract: A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.Type: ApplicationFiled: May 31, 2012Publication date: July 4, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Min Lin, Chau-Jie Zhan, Tao-Chih Chang
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Patent number: 8415795Abstract: A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.Type: GrantFiled: April 18, 2011Date of Patent: April 9, 2013Assignee: Industrial Technology Research InstituteInventors: Yu-Min Lin, Chau-Jie Zhan, Su-Tsai Lu
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Publication number: 20120161336Abstract: A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.Type: ApplicationFiled: April 18, 2011Publication date: June 28, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Min Lin, Chau-Jie Zhan, Su-Tsai Lu
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Publication number: 20120125669Abstract: A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.Type: ApplicationFiled: January 31, 2012Publication date: May 24, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsung-Fu Tsai, Chau-Jie Zhan, Jing-Yao Chang, Tao-Chih Chang
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Patent number: 8130509Abstract: A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.Type: GrantFiled: June 12, 2009Date of Patent: March 6, 2012Assignee: Industrial Technology Research InstituteInventors: Tsung-Fu Tsai, Chau-Jie Zhan, Jing-Yao Chang, Tao-Chih Chang
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Publication number: 20110227190Abstract: The invention provides an electronic device package structure and method of fabrication thereof. The electronic device package structure includes a chip having an active surface and a bottom surface. A dielectric layer is disposed on the active surface of the chip. At least one trench is formed through the dielectric layer. A first protection layer covers the dielectric layer and sidewalls of the trench. A second protection layer covers the first protection layer, filling the trench.Type: ApplicationFiled: September 27, 2010Publication date: September 22, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tao-Chih Chang, Su-Tsai Lu, Jing-Yao Chang, Chau-Jie Zhan
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Publication number: 20110156253Abstract: A dished micro-bump structure with self-aligning functions is provided. The micro-bump structure takes advantage of the central concavity for achieving the accurate alignment with the corresponding micro-bumps.Type: ApplicationFiled: September 17, 2010Publication date: June 30, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsung-Fu Tsai, Tao-Chih Chang, Chau-Jie Zhan
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Publication number: 20100207266Abstract: A chip package structure including a substrate, a plurality of electrodes, a chip, and a plurality of bumps is provided. Each of the electrodes has a bottom portion and an annular element, wherein the bottom portion is disposed on the substrate, the annular element is disposed on the bottom portion, and the bottom portion and the annular element define a containing recess. The chip is disposed above the substrate and has an active surface facing the substrate and a plurality of pads disposed on the active surface. The bumps are respectively disposed on the pads and respectively inserted into the containing recesses. The melting point of the electrodes is higher than that of the bumps. A chip package method is also provided.Type: ApplicationFiled: April 21, 2009Publication date: August 19, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tao-Chih Chang, Su-Tsai Lu, Chau-Jie Zhan, Chun-Chih Chuang, Jing-Ye Juang
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Publication number: 20100163292Abstract: A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.Type: ApplicationFiled: June 12, 2009Publication date: July 1, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsung-Fu Tsai, Chau-Jie Zhan, Jing-Yao Chang, Tao-Chih Chang