Abstract: One or more specific versions disclosed herein includes a power tong for rotating tubulars in wellbore operations, comprising: a gear shaft having a non-threaded portion and a flange; a gear rotatably connected to the gear shaft; and a tong plate having an inner surface and an outer surface, wherein the flange is removably coupled to the inner surface of the tong plate.

Abstract: One or more specific versions disclosed herein includes a power tong for rotating tubulars in wellbore operations, including: an upper tong plate, a lower tong plate, a gear train disposed between the upper tong plate and the lower tong plate; and a strut removably coupled to the lower tong plate, the upper tong plate, or both.

Abstract: One or more specific versions disclosed herein includes a power tong for rotating tubulars in wellbore operations comprising: a gear shaft having a non-threaded portion; a gear rotatably connected to the non-threaded portion of the gear shaft; a tong plate having an inner surface, an outer surface, and a gear shaft aperture, wherein an end of the non-threaded portion is disposed in the gear shaft aperture; and a shaft retainer that is removably coupled to the tong plate and abutted against the end of the non-threaded portion.

Abstract: A method for producing porous nanofibers having tunable meso- and micropores, and the articles produced by the method. In some embodiments, the method comprises electrospinning a polymer blend comprising polyacrylonitrile and a sulfonated polymer dissolved in a solvent to form a fibers; heat treating the mat or web of fibers sequentially at first, second, and optionally third temperatures; and optionally treating the heat treated fibers with an oxidizing agent.

Abstract: A controller and a method for interfacing between a host and storage medium. A storage medium interface includes CH0 circuitry for performing a CH0 process to access a buffer memory on behalf of the storage medium. A host interface includes CH1 circuitry for performing a CH1 process to access the buffer memory on behalf of the host. Access to the buffer memory is arbitrated in sequential tenures to each channel of the multi-channel bus within a maximum arbitration round trip time defined by the time taken by the storage medium to move a distance corresponding to N sectors in which N is greater than one. In the CH0 tenure, the CH0 process transfers data corresponding to N sectors of the storage medium in a multi-sector burst. The length of the tenure of the CH0 channel is pre-designated so that the multi-sector burst is completed within the CH0 tenure.

Abstract: A controller and a method for interfacing between a host and storage medium. A storage medium interface includes CH0 circuitry for performing a CH0 process to access a buffer memory on behalf of the storage medium. A host interface includes CH1 circuitry for performing a CH1 process to access the buffer memory on behalf of the host. Access to the buffer memory is arbitrated in sequential tenures to each channel of the multi-channel bus within a maximum arbitration round trip time defined by the time taken by the storage medium to move a distance corresponding to N sectors in which N is greater than one. In the CH0 tenure, the CH0 process transfers data corresponding to N sectors of the storage medium in a multi-sector burst. The length of the tenure of the CH0 channel is pre-designated so that the multi-sector burst is completed within the CH0 tenure.

Abstract: A computer-implemented method, system, and computer program product for a web-based integrated test and debugging system is provided. The method includes configuring a proxy widget on a server to communicate with a debug widget on a browser, and configuring the proxy widget to communicate with an integrated development environment (IDE) external to the server. The method also includes running a process on the server associated with one or more process-control widgets on the browser. The method further includes polling the IDE via the proxy widget to access a debug and test infrastructure of the IDE for debug data associated with the process, and relaying the debug data associated with the process from the proxy widget to the debug widget to provide web-based integration of testing and debugging on the browser while the process is running on the server.

Abstract: A computer-implemented method, system, and computer program product for a web-based integrated test and debugging system is provided. The method includes configuring a proxy widget on a server to communicate with a debug widget on a browser, and configuring the proxy widget to communicate with an integrated development environment (IDE) external to the server. The method also includes running a process on the server associated with one or more process-control widgets on the browser. The method further includes polling the IDE via the proxy widget to access a debug and test infrastructure of the IDE for debug data associated with the process, and relaying the debug data associated with the process from the proxy widget to the debug widget to provide web-based integration of testing and debugging on the browser while the process is running on the server.

Abstract: A temperature setpoint circuit comprises bipolar transistors Q1 and Q2 which receive currents I1 and I2 at their respective collectors and are operated at unequal current densities, with a resistance R1 connected between their bases such that the difference in their base-emitter voltages (?Vbe) appears across R1. An additional PTAT current I3 is maintained in a constant ratio to I1 and I2 and provided to the collector of Q2 while Q2 is off, and is not provided while Q2 is on. The circuit is arranged such that Q2 is turned on and conducts a current equal to Ia when: ?Vbe=(kT/q)ln(NI1/Ia), where Ia=I2+I3, the temperature T at which ?Vbe=(kT/q)ln(NI1/Ia) being the circuit's setpoint temperature, such that the switching of current I3 provides hysteresis for the setpoint temperature which is approximately constant over temperature.

Abstract: A multiple differential amplifier system and method for transconductance mismatch compensation which in a first phase connects to a differential switched input of a null amplifier, the differential signal input of the main amplifier, inverted, for compensating for offset errors and transconductance mismatches in the null amplifier; and storing in a null storage device connected to an auxiliary input of the null amplifier the output of the null amplifier representing the compensation for the offset error and transconductance mismatch of the null amplifier; and in a second phase connecting the differential switched input of the null amplifier to the differential feedback input of the main amplifier and storing in the main storage device connected to an auxiliary input of the main amplifier the output of the null amplifier representing the compensation for the main amplifier offset error and transconductance mismatch.

Abstract: A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.