Abstract: A method for capacitance extraction includes: performing a first capacitance extraction on one or more first regions of a semiconductor layout; performing a second capacitance extraction on one or more second regions of the semiconductor layout, a resolution of the second capacitance extraction being less than a resolution of the first capacitance extraction; constructing a netlist for the semiconductor layout based on results of the first capacitance extraction and of the second capacitance extraction; and modifying the semiconductor layout based on the netlist. The modified semiconductor layout is used to fabricate an integrated circuit.

Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.

Abstract: An integrated circuit (IC) design system includes a processor; and a non-transitory computer readable medium connected to the processor. The non-transitory computer readable medium is configured to store a configuration file containing a custom IC design parameter, to store a process design kit (PDK) containing a default IC design parameter, and to store instructions for execution by the processor. The instructions for execution by the process include instructions for extracting the custom IC design parameter from the configuration file. The instructions for execution by the process further include instructions for overwriting the default IC design parameter in the PDK with the custom IC design parameter. The instructions for execution by the process further include instructions for creating an IC design file using a module in the PDK using the custom IC design parameter in place of the default IC design parameter.

Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.

Abstract: An integrated circuit (IC) design system includes a processor; and a non-transitory computer readable medium connected to the processor. The non-transitory computer readable medium is configured to store a configuration file containing a custom IC design parameter, to store a process design kit (PDK) containing a default IC design parameter, and to store instructions for execution by the processor. The instructions for execution by the process include instructions for extracting the custom IC design parameter from the configuration file. The instructions for execution by the process further include instructions for overwriting the default IC design parameter in the PDK with the custom IC design parameter. The instructions for execution by the process further include instructions for creating an IC design file using a module in the PDK using the custom IC design parameter in place of the default IC design parameter.

Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.

Abstract: An integrated circuit design method includes extracting a custom IC design parameter from a configuration file using a design customization module (DCM) and creating an IC design file with a module in a processor design kit (PDK) using the custom IC design parameter.

Abstract: An integrated circuit design method includes extracting a custom IC design parameter from a configuration file using a design customization module (DCM) and creating an IC design file with a module in a processor design kit (PDK) using the custom IC design parameter.

Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.

Abstract: An apparatus comprises two n-type metal oxide semiconductor (MOS) devices formed next to each other. Each n-type MOS device further includes a pair of face-to-face diodes formed in an isolation ring. A method of modeling the apparatus comprises reusing four-terminal MOS device models in standard cell libraries and combining the four-terminal MOS device model and the isolation ring model into a 4T MOS plus isolation ring model. The method of modeling the apparatus further comprises adding a dummy device between a body contact of the first n-type MOS device and a body contact of the second n-type MOS device.

Abstract: An apparatus comprises two n-type metal oxide semiconductor (MOS) devices formed next to each other. Each n-type MOS device further includes a pair of face-to-face diodes formed in an isolation ring. A method of modeling the apparatus comprises reusing four-terminal MOS device models in standard cell libraries and combining the four-terminal MOS device model and the isolation ring model into a 4T MOS plus isolation ring model. The method of modeling the apparatus further comprises adding a dummy device between a body contact of the first n-type MOS device and a body contact of the second n-type MOS device.

Abstract: A thermal module suitable for cooling a heat generating element within a casing of an electronic apparatus includes a fan, a heat sink and a heat pipe. The fan is mounted within the casing for generating airflow to an opening of the casing. The heat sink is mounted within the casing between the opening of the casing and the fan, such that the airflow generated by the fan passes through the heat sink and then flows out of the opening. The heat pipe contacts the heat generating element, extends from the heat generating element to the heat sink, and extends along a periphery of the fan to contact the heat generating element again.

Abstract: A thermal module suitable for cooling a heat generating element within a casing of an electronic apparatus includes a fan, a heat sink and a heat pipe. The fan is mounted within the casing for generating airflow to an opening of the casing. The heat sink is mounted within the casing between the opening of the casing and the fan, such that the airflow generated by the fan passes through the heat sink and then flows out of the opening. The heat pipe contacts the heat generating element, extends from the heat generating element to the heat sink, and extends along a periphery of the fan to contact the heat generating element again.

Abstract: A heat dissipating module includes a releasing member, a heat pipe, which has a first end connected to the releasing member and a second end attached to the top surface of a thermal chip on a circuit board, and a fastening member, which has a protruded arch portion that defines an arch chamber that accommodates the second end of the heat pipe, two press portions respectively extended from two opposite lateral sides of the protruded arch portion and pressed on the top surface of the thermal chip, and a plurality of hook portions respectively extended from the press portions and hooked on the bottom edge of the circuit board.

Abstract: A heat dissipating module includes a releasing member, a heat pipe, which has a first end connected to the releasing member and a second end attached to the top surface of a thermal chip on a circuit board, and a fastening member, which has a protruded arch portion that defines an arch chamber that accommodates the second end of the heat pipe, two press portions respectively extended from two opposite lateral sides of the protruded arch portion and pressed on the top surface of the thermal chip, and a plurality of hook portions respectively extended from the press portions and hooked on the bottom edge of the circuit board.

Abstract: The present invention provides a package device for reducing the electromagnetic/radio frequency interference, which includes a first substrate with a shielding structure on the under surface of the first substrate, and an insulating layer on the shielding structure. The first substrate includes a through hole that is filled with the conductor therein. A plurality of lead-frames located on the bottom surface of the first substrate. A second substrate located above between the two lead-frames. Then, the molding compound encapsulated to cover the above structures to form a package device. Therefore, the shielding path of the package device is constructed of the plurality of lead-frames, the conductor within the first substrate, the shielding structure, and the grounded to discharge the electromagnetic/radio frequency out of the package device, thus, the electromagnetic/radio frequency interference for the package device can be reduced.

Abstract: A method for preventing the overflowing of the molding compound is disclosed. The method provides a substrate that having at least a pair of outer leads. By the pressed downward the pair of outer leads as the thimble point, the substrate can contact with the mold completely without any gap therebetween, thus, the overflowing of the molding compound would not be occurred.

Abstract: A power module package structure is disclosed. The control circuits are fabricated on a circuit plate, instead of fabricating them directly on a main substrate. The fabrication cost is reduced because the size of the substrate is shrunk. Furthermore, the power chips are placed on a material with high thermal conductivity. The heat produced from the power chips can be transmitted quickly. Thus, the reliability of the power module package can be improved.

Abstract: The present invention provides a package structure, which includes a substrate, wherein the circuit has been configured within the substrate; a lead-frame having lead on the first surface of the substrate; at least one first electronic device located on the lead-frame; a second electronic device located on the first surface of the substrate whose the circuit has been configured therein; a plurality of conductive wires, which used for electrically coupling the first electronic device and second electronic device, and the second electronic device with the lead-frame; a molding compound, which used to seal the portion of substrate, the first electronic device, the second electronic device, and the portion of the lead-frame; and a metal plate, which located on the second surface of the substrate, and used to remove the heat that is generated from the first electronic device.