Abstract: A method for forming a shallow trench isolation using a SiON anti-reflective coating which eliminates water spot defects. The method begins by providing a substrate. A pad oxide layer is formed over the substrate. A silicon nitride layer is formed on the pad oxide layer. A silicon oxynitride layer is formed on the silicon nitride layer. A photoresist mask, having an opening, is formed over the silicon oxynitride layer. The silicon oxynitride layer, the silicon nitride layer, the pad oxide layer, and the substrate are etched through the opening, forming a trench. The photoresist mask is removed. In the key step, the silicon oxynitride layer is removed. Then, a thin silicon oxide layer is grown and a silicon oxide layer is deposited and planarized to form a shallow trench isolation.

Abstract: A process for forming a low resistance, titanium disilicide layer, on regions of a MOSFET device, has been developed. The process features the deposition of a capping, silicon oxide layer, on first phase, high resistance, titanium disilicide regions. The capping, silicon oxide layer, featuring a compressive stress, reduces the risk of titanium disilicide regions, formed with a tensile stress, from adhesion loss, or peeling, from underlying regions of the MOSFET device, such as from the top surface of a narrow width, polysilicon gate structure. In addition the capping silicon oxide layer protects underlying titanium disilicide regions from the ambient used during the anneal cycle used to convert the first phase, high resistance, titanium disilicide region, to the second phase, low resistance, titanium disilicide region.