Patents by Inventor Chauncey L. Everett

Chauncey L. Everett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4490632
    Abstract: A noninverting amplifier circuit for one propagation delay complex logic gates. The noninverting amplifier circuit is compatible with field effect transistor logic, including depletion-mode Schottky barrier field effect transistor (MESFET) inverting logic, gates. The basic noninverting amplifier circuit, utilizes field effect transistors (FET) and diodes, and comprises input interface means for receiving an input voltage signal, amplifier means for providing noninverted amplification of the input voltage signal, and buffer means for driving, and shifting the voltage level of the amplified input voltage signal. In another embodiment, additional circuit means for enabling performance of the "AND" logic function is included in the basic noninverting amplifier circuit. In a third embodiment, additional circuit means for enabling performance of the "OR" logic function is included in the basic noninverting amplifier circuit.
    Type: Grant
    Filed: November 23, 1981
    Date of Patent: December 25, 1984
    Assignee: Texas Instruments Incorporated
    Inventors: Chauncey L. Everett, Theodore W. Houston, Henry M. Darley
  • Patent number: 4484310
    Abstract: A static-type noninverting memory cell for one propagation delay memory circuits which is compatible with inverting and noninverting field effect transistor logic, such as, for example, depletion mode Schottky barrier field effect transistor (MESFET) inverting logic. The basic memory cell utilizes field effect transistors and a diode, and comprises an input for receiving an input signal, a transistor operating in a switching mode and connected to the input for registering the logic state of the input signal, a memory section which includes a pair of transistors each of whose respective gates are connected to the sources, a diode interposed therebetween, and a logic state-holding transistor for retaining a stored logic state of the registered input signal, and an output terminal connected between the diode and one of the transistor pair of the memory section from which the stored logic state within the memory section may be sensed.
    Type: Grant
    Filed: March 29, 1982
    Date of Patent: November 20, 1984
    Assignee: Texas Instruments Incorporated
    Inventors: Chauncey L. Everett, Theodore W. Houston, Henry M. Darley