Patents by Inventor Chauncey S. Miller

Chauncey S. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4606045
    Abstract: Apparatus, and a related method, for fast carrier acquisition in a modem. The apparatus includes circuitry to speed carrier acquisition by the determination of which of two alternate phasors is being received during a baud synchronization period of a signal preamble before data transmission. Another aspect of the invention involves the use of a complex matched filter for the determination of the start of an equalizer training sequence in the signal preamble. The output of the matched filter exhibits a deep null at the start of the training sequence, since the beginning of the sequence bears an inverse relationship to the end of the preceeding baud synchronization period.
    Type: Grant
    Filed: March 16, 1984
    Date of Patent: August 12, 1986
    Assignee: TRW Inc.
    Inventor: Chauncey S. Miller
  • Patent number: 4462108
    Abstract: Apparatus, and a related method, for fast carrier acquisition in a modem. The apparatus includes circuitry to speed carrier acquisition by the determination of which of two alternate phasors is being received during a baud synchronization period of a signal preamble before data transmission. Another aspect of the invention involves the use of a complex matched filter for the determination of the start of an equalizer training sequence in the signal preamble. The output of the matched filter exhibits a deep null at the start of the training sequence, since the beginning of the sequence bears an inverse relationship to the end of the preceeding baud synchronization period.
    Type: Grant
    Filed: August 2, 1982
    Date of Patent: July 24, 1984
    Assignee: TRW Inc.
    Inventor: Chauncey S. Miller
  • Patent number: 4453259
    Abstract: Method and apparatus for providing a sequence of digitized samples to a modem in substantial synchronism with the incoming signal baud rate, but without using a variable sampling frequency. An incoming signal is sampled at a fixed rate, stored temporarily in a buffer memory, and then interpolated using a digital interpolation filter to provide a sequence of interpolated samples that are equivalent to those that would have been obtained if a variable-frequency sampling rate had been used. Any relative delay between the samples supplied to the modem and the baud rate is sensed and accumulated in an up/down counter. Then the accumulated delay stored in the counter is used to control the selection of coefficients for the interpolation filter.
    Type: Grant
    Filed: April 20, 1982
    Date of Patent: June 5, 1984
    Assignee: TRW Inc.
    Inventor: Chauncey S. Miller
  • Patent number: 4011408
    Abstract: In delay module means, an input signal is divided into a number of subsignals, each separated from the others by a selected time delay. In a primary module the subsignals are selectively weighted and combined with the input signal. In the inverse module, the signal is similarly differentially delayed and weighted, and subtracted from the input by feedback loop means. Audio signal scrambling is accomplished by passing the signal through one or more primary and/or inverse modules in series; descrambling is accomplished by passing the scrambled signal through a complementary series of modules. Frequency translation and/or inversion is also applied for applications requiring increased security.
    Type: Grant
    Filed: December 17, 1975
    Date of Patent: March 8, 1977
    Assignee: TRW Inc.
    Inventor: Chauncey S. Miller, III
  • Patent number: 3964060
    Abstract: A parallel or serial analog-to-digital converter utilizing both Gunn effect devices and field effect transistors. The converters are based on a differential pair of amplifiers consisting of two or more Gunn effect devices, one of which is biased close to the knee of the current-voltage characteristic before the negative resistance region. Hence a clock pulse will bias one of the devices into the negative resistance region while the other device is now biased close to the knee to be able to respond to the analog signal. This is due to the fact that both devices are biased by a common constant current source, including a field effect transistor.
    Type: Grant
    Filed: July 2, 1975
    Date of Patent: June 15, 1976
    Assignee: TRW Inc.
    Inventors: Dale H. Claxton, Chauncey S. Miller