Abstract: A driver device for providing multi-resolution modes for a display device, a liquid crystal display panel for example, is provided in this invention. This display driver includes a pixel circuit and a gate driving circuit. The gate driving circuit is coupled to the pixel circuit via a plurality of gate lines and determines either an original gate driving signal or a target gate driving signal to be the gate drive signal in response to the gate control signal. Wherein a switch circuit is configured for switching between the original driving signal and the target gate driving signal via a plurality of switches corresponding to shift registers therein. A source driving circuit is further incorporated in this present invention to configure a multi-resolution display device, coupled to the pixel circuit via a plurality of source lines and outputs the source driving signal in response to a source control signal.

Abstract: A display circuit for a liquid crystal display panel is provided. The display circuit comprises a control circuit, a data driving circuit, a partial display mode driving circuit, a scanning circuit, and a liquid crystal display panel. When the LCD works in the partial display mode, the control circuit will stop sending out the shift clock signal for controlling the data driving circuit for the non-display area and will make both ends of the pixel electrodes in the non-display area equipotential. Hence, there is no complicated operation for the data driving circuit, and power consumption and thus be reduced.

Abstract: A method of charging a liquid crystal display (LCD) device that includes providing a plurality of scan lines, providing a plurality of video lines formed orthogonal to the scan lines, providing a plurality of cells, each cell including a transistor and a capacitor coupled to the transistor, each of the cells being formed at an intersection of the scan lines and video lines, providing a periodic signal for writing video data into the LCD device, charging the plurality of cells having first-type transistors during a first half cycle of the periodic signal until a first voltage level of the periodic signal is reached, charging the plurality of cells having second-type transistors during a second half cycle of the periodic signal until a second voltage level of the periodic signal is reached, and discharging the plurality of cells to a predetermined voltage level.

Abstract: A layout method for improving image quality, suitable for use in a display. The display has a plurality of pixels and a plurality of control circuits. The pixels and the control circuits are divided into several sections, each having a plurality of data lines connected to a plurality of image input lines. The layout method is characterized in that between two consecutive sections, the image input line connected to the last data line of the front section is located in proximity of the data line connected to the image input line connected to the first data line of the rear section. Therefore, loads applied to the image input lines of the consecutive sections are not too much different from each other, and the image non-uniformity is thus improved.

Abstract: A display circuit for a liquid crystal display panel is provided. The display circuit comprises a control circuit, a data driving circuit, a partial display mode driving circuit, a scanning circuit, and a liquid crystal display panel. When the LCD works in the partial display mode, the control circuit will stop sending out the shift clock signal for controlling the data driving circuit for the non-display area and will make both ends of the pixel electrodes in the non-display area equipotential. Hence, there is no complicated operation for the data driving circuit, and power consumption and thus be reduced.

Abstract: The present invention provides a color liquid crystal display device in which a color filter layer is formed on an array substrate. The array substrate includes a scan line and a data line forming a pixel, on which a thin film transistor is formed, and a pixel electrode is connected to the thin film transistor. A black matrix layer is formed on the array substrate. A black matrix frame is formed around the periphery of the black matrix layer. A color filter layer is formed on the array substrate and the black matrix layer, and extends to cover the black matrix frame.

Abstract: A storage capacitor structure of a planar display is disclosed. The storage capacitor includes a substrate, a bottom electrode, an insulator, and a top electrode. The bottom electrode or top electrode has an uneven surface toward the insulator interposed between the two electrodes in order to increase the capacitance of the storage capacitor structure. A method for fabricating such storage capacitor structure is also disclosed. It includes steps of providing a substrate; and forming a bottom electrode, an insulator, and a top electrode in sequence. The bottom electrode or the top electrode has the uneven surface by an etching step.

Abstract: A voltage level shifter includes a front stage circuit periodically generating a first control signal and a second control signal in response to a first input clock signal and a second input clock signal complementary to the first input clock signal; a switch circuit including two PMOS transistors connected between a maximum voltage and a minimum voltage in series, wherein a third control signal is outputted from a conjunction of the two PMOS transistors, and the first and second control signals are coupled to the gate electrodes of the two PMOS transistors, respectively; and a driving circuit receiving the third control signal and outputting an output clock signal having a peak-to-peak value larger than a peak-to-peak value of the input clock signal. The voltage level shifter is implemented by essentially PMOS transistors.

Abstract: A method of charging a liquid crystal display (LCD) device that includes providing a plurality of scan lines, providing a plurality of video lines formed orthogonal to the scan lines, providing a plurality of cells, each cell including a transistor and a capacitor coupled to the transistor, each of the cells being formed at an intersection of the scan lines and video lines, providing a periodic signal for writing video data into the LCD device, charging the plurality of cells having first-type transistors during a first half cycle of the periodic signal until a first voltage level of the periodic signal is reached, charging the plurality of cells having second-type transistors during a second half cycle of the periodic signal until a second voltage level of the periodic signal is reached, and discharging the plurality of cells to a predetermined voltage level.

Abstract: A driver device for providing multi-resolution modes for a display device, a liquid crystal display panel for example, is provided in this invention. This display driver includes a pixel circuit and a gate driving circuit. The gate driving circuit is coupled to the pixel circuit via a plurality of gate lines and determines either an original gate driving signal or a target gate driving signal to be the gate drive signal in response to the gate control signal. Wherein a switch circuit is configured for switching between the original driving signal and the target gate driving signal via a plurality of switches corresponding to shift registers therein. A source driving circuit is further incorporated in this present invention to configure a multi-resolution display device, coupled to the pixel circuit via a plurality of source lines and outputs the source driving signal in response to a source control signal.

Abstract: The present invention provides a color liquid crystal display device in which a color filter layer is formed on an array substrate. The array substrate includes a scan line and a data line forming a pixel, on which a thin film transistor is formed, and a pixel electrode is connected to the thin film transistor. A black matrix layer is formed on the array substrate. A black matrix frame is formed around the periphery of the black matrix layer. A color filter layer is formed on the array substrate and the black matrix layer, and extends to cover the black matrix frame.

Abstract: A pixel structure of a thin-film transistor liquid crystal display. A storage capacitor is formed by simultaneously defining a doped polysilicon layer, a dielectric layer and shielding metal layer and a source/drain region of a low-temperature polysilicon thin-film transistor. The shielding metal layer is formed on the doped polysilicon layer and is electrically connected to a pixel electrode. As the area occupied by the shielding metal layer is the area of the storage capacitor, the aperture ratio is greatly enhanced.

Abstract: A layout method for improving image quality, suitable for use in a display. The display has a plurality of pixels and a plurality of control circuits. The pixels and the control circuits are divided into several sections, each having a plurality of data lines connected to a plurality of image input lines. The layout method is characterized in that between two consecutive sections, the image input line connected to the last data line of the front section is located in proximity of the data line connected to the image input line connected to the first data line of the rear section. Therefore, loads applied to the image input lines of the consecutive sections are not too much different from each other, and the image non-uniformity is thus improved.

Abstract: A voltage level shifter includes a front stage circuit periodically generating a first control signal and a second control signal in response to a first input clock signal and a second input clock signal complementary to the first input clock signal; a switch circuit including two PMOS transistors connected between a maximum voltage and a minimum voltage in series, wherein a third control signal is outputted from a conjunction of the two PMOS transistors, and the first and second control signals are coupled to the gate electrodes of the two PMOS transistors, respectively; and a driving circuit receiving the third control signal and outputting an output clock signal having a peak-to-peak value larger than a peak-to-peak value of the input clock signal. The voltage level shifter is implemented by essentially PMOS transistors.

Abstract: A scan driving circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit receives a driving signal and outputs the driving signal to a first scan line of the active matrix via a first output terminal after a predetermined time delay. The second sub-circuit is electrically connected to the first sub-circuit, receives the driving signal transferred from a second output terminal of the first sub-circuit, and outputs the driving signal to a second scan line of an active matrix after the predetermined time delay. Furthermore, the first sub-circuit includes a unidirectional conducting device electrically connected between the first output terminal and the second output terminal.

Abstract: A display panel includes a substrate, a pixel matrix, a driving circuit and an embedded test circuit. The pixel matrix is formed on the substrate. The driving circuit is formed on the substrate and electrically connected to the pixel matrix for controlling the pixel matrix in either a switching-on or switching-off state. The embedded test circuit is formed on the substrate and electrically connected to the driving circuit for testing the driving circuit and outputting a test result.

Abstract: A pixel structure of a thin-film transistor liquid crystal display. A storage capacitor is formed by simultaneously defining a doped polysilicon layer, a dielectric layer and shielding metal layer and a source/drain region of a low-temperature polysilicon thin-film transistor. The shielding metal layer is formed on the doped polysilicon layer and is electrically connected to a pixel electrode. As the area occupied by the shielding metal layer is the area of the storage capacitor, the aperture ratio is greatly enhanced.

Abstract: A storage capacitor structure of a planar display is disclosed. The storage capacitor includes a substrate, a bottom electrode, an insulator, and a top electrode. The bottom electrode or top electrode has an uneven surface toward the insulator interposed between the two electrodes in order to increase the capacitance of the storage capacitor structure. A method for fabricating such storage capacitor structure is also disclosed. It includes steps of providing a substrate; and forming a bottom electrode, an insulator, and a top electrode in sequence. The bottom electrode or the top electrode has the uneven surface by an etching step.