Patents by Inventor Chauo-Min Chen

Chauo-Min Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock regeneration method, reference-less receiver, and crystal-less system
    Patent number: 8724762
    Abstract: A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: May 13, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Yen-Yin Huang, Chauo-Min Chen, Kuan-Yu Chen, Yu-Sheng Yi, Ming-Shih Yu
  • CLOCK REGENERATION METHOD, REFERENCE-LESS RECEIVER, AND CRYSTAL-LESS SYSTEM
    Publication number: 20130010909
    Abstract: A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.
    Type: Application
    Filed: July 4, 2011
    Publication date: January 10, 2013
    Inventors: Yen-Yin Huang, Chauo-Min Chen, Kuan-Yu Chen, Yu-Sheng Yi, Ming-Shih Yu
  • Signal delay apparatus for providing exact delay amount, memory apparatus utilizing the signal delay apparatus, and signal delay method
    Patent number: 8242824
    Abstract: A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: August 14, 2012
    Assignee: Faraday Technology Corp.
    Inventors: Yen-Yin Huang, Chih-Hsien Lin, Chauo-Min Chen, Ming-Shih Yu
  • SIGNAL DELAY APPARATUS FOR PROVIDING EXACT DELAY AMOUNT, MEMORY APPARATUS UTILIZING THE SIGNAL DELAY APPARATUS, AND SIGNAL DELAY METHOD
    Publication number: 20120194242
    Abstract: A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 2, 2012
    Inventors: Yen-Yin Huang, Chih-Hsien Lin, Chauo-Min Chen, Ming-Shih Yu