Abstract: A flip-chip package comprises a substrate with an opening. A dummy die is disposed onto the substrate corresponding to the opening so as to form a composite chip carrier with a chip cavity. The dummy die has a redistribution layer which includes a plurality of flip-chip pads for flip-chip connection of a chip and a plurality of connecting pads around the dummy die for connecting the substrate. The dummy die mounts at least a chip by flip chip connection for being an electrical interface medium between the chip and the substrate in order to achieve thinner package thickness, high heat dissipation, fine pitch flip-chip mounting and eliminating flip-chip stress on the chip.

Abstract: A stack type flip-chip package is described, including a substrate board, a first chip, a second chip, a packaging material and a heat sink. The substrate board has bump contacts and line contacts thereon, wherein the bump contacts connect with the bonding pads on the active surface of the first chip via bumps. The back surface of the first chip has a redistribution circuit thereon including bump pads and line pads exposed by a passivation layer, wherein the bump pads connect with the bonding pads of the second chip via bumps, and the line pads are connected to the line contacts via conductive wires. The packaging material encloses the first chip and the conductive wires, but may expose the back surface of the second chip, to which a heat sink can be directly bonded.

Abstract: A flip chip on leadframe package includes a leadframe, a non-flow underfilling material and a flip chip. The leadframe has a plurality of inner leads. Each inner lead has an upper surface and a lower surface. A coating region is defined on the upper surfaces. The non-flow underfilling material is formed on the coating region. The chip has an active surface with a plurality of bumps. The bumps pass through the non-flow underfilling material to be connected to the coating region of the upper surfaces. Only the leadframe inside the coating region are wettable with the bumps for controlling the collapse of the bumps.

Abstract: A flip-chip package comprises a substrate with an opening. A dummy die is disposed onto the substrate corresponding to the opening so as to form a composite chip carrier with a chip cavity. The dummy die has a redistribution layer which includes a plurality of flip-chip pads for flip-chip connection of a chip and a plurality of connecting pads around the dummy die for connecting the substrate. The dummy die mounts at least a chip by flip chip connection for being an electrical interface medium between the chip and the substrate in order to achieve thinner package thickness, high heat dissipation, fine pitch flip-chip mounting and eliminating flip-chip stress on the chip.

Abstract: A multi-chip stack flip-chip package comprises a substrate and a chip assembly on the substrate. The chip assembly includes a dummy chip and a flip chip. The dummy chip has a redistribution layer that has a plurality of bump pads for mounting the flip chip, a plurality of peripheral pads for electrically connecting to the substrate, and a plurality of integrated circuit traces connecting the bump pads with the peripheral pads. The dummy chip is disposed between the flip chip and the substrate as an electrically connecting interface between the flip chip and the substrate for multi-chip flip-chip stack and fine pitch flip-chip mounting.

Abstract: A stack type flip-chip package is described, including a substrate board, a first chip, a second chip, a packaging material and a heat sink. The substrate board has bump contacts and line contacts thereon, wherein the bump contacts connect with the bonding pads on the active surface of the first chip via bumps. The back surface of the first chip has a redistribution circuit thereon including bump pads and line pads exposed by a passivation layer, wherein the bump pads connect with the bonding pads of the second chip via bumps, and the line pads are connected to the line contacts via conductive wires. The packaging material encloses the first chip and the conductive wires, but may expose the back surface of the second chip, to which a heat sink can be directly bonded.

Abstract: A thin type ball grid array package is provided. A composite substrate for the package is consisted of a wiring board and a dummy die. The wiring board has an opening through upper and lower surfaces thereof. The dummy chip is attached to one surface of the wiring board, and covers the opening to form a chip cavity for accommodating an integrated circuit chip. The wiring board has a step with a plurality of connecting pads in the opening. The integrated circuit chip is attached to the dummy die and electrically connected to the connecting pads of the wiring board. A package body is formed in the chip cavity.

Abstract: A signal transmission plate used in an assembly package includes at least one insulating layer, at least one layout wire layer formed on the insulating layer, and a solder mask layer formed on the layout wire layer. The solder mask layer exposes partial area of the layout wire layer at the center and peripheries of the signal transmission plate to form a plurality of die bonding pads and a plurality of wire bonding pads.

Abstract: A stack type flip-chip package that utilizes a redistribution circuit on the back of a chip to serve as a bridge for connecting with other chips. The package includes at least a substrate, a first chip, a second chip, some underfill material and some packaging material. The substrate has a plurality of bump contacts and a plurality of line contacts thereon. The first chip has an active surface with a plurality of first bonding pads thereon. The back surface of the first chip has a redistribution circuit. The redistribution circuit has a plurality of bump pads and a plurality of line pads thereon. The second chip has an active surface with a plurality of second bonding pads thereon. Bumps are positioned between the bump contacts and the first bonding pads and between the bump pads and the second bonding pads. Conductive wires connect the line contacts and the line pads. The underfill material fills the space between the chip and the substrate and the gap between the first and the second chips.

Abstract: A multi-chip stack flip-chip package comprises a substrate and a chip assembly on the substrate. The chip assembly includes a dummy chip and a flip chip. The dummy chip has a redistribution layer that has a plurality of bump pads for mounting the flip chip, a plurality of peripheral pads for electrically connecting to the substrate, and a plurality of integrated circuit traces connecting the bump pads with the peripheral pads. The dummy chip is disposed between the flip chip and the substrate as an electrically connecting interface between the flip chip and the substrate for multi-chip flip-chip stack and fine pitch flip-chip mounting.

Abstract: An assembly package includes a substrate, a first die, at least one signal transmission plate, at least one second die, a plurality of conductive wires, and a molding compound. The first die is electrically connected with the substrate using flip-chip bonding. The signal transmission plate is provided on the first die and includes an insulating layer, a layout wire layer, and a solder mask layer. The layout wire layer is formed on the insulating layer, and the solder mask layer is formed on the layout wire layer. The solder mask exposes partial area of the layout wire layer at the center and peripheries of the signal transmission plate to form a plurality of die bonding pads and a plurality of wire bonding pads. The second die is electrically connected with the die bonding pads using flip-chip bonding, and the wire bonding pads are electrically connected with the substrate via the conductive wires so that the signals from the second die are transmitted to the substrate.

Abstract: A stacked package includes a substrate, a first die, at least one signal transmission plate, at least one second die, a plurality of conductive wires, and a molding compound. The first die is electrically connected with the substrate using flip-chip bonding. The signal transmission plate is provided on the first die and includes an insulating layer, a layout wire layer, and a solder mask layer. The layout wire layer is formed on the insulating layer, and the solder mask layer is formed on the layout wire layer. The solder mask exposes partial area of the layout wire layer at the center and peripheries of the signal transmission plate to form a plurality of die bonding pads and a plurality of wire bonding pads. The second die is electrically connected with the die bonding pads using flip-chip bonding, and the wire bonding pads are electrically connected with the substrate via the conductive wires so that the signals from the second die are transmitted to the substrate.

Abstract: A stack type flip-chip package that utilizes a redistribution circuit on the back of a chip to serve as a bridge for connecting with other chips. The package includes at least a substrate, a first chip, a second chip, some underfill material and some packaging material. The substrate has a plurality of bump contacts and a plurality of line contacts thereon. The first chip has an active surface with a plurality of first bonding pads thereon. The back surface of the first chip has a redistribution circuit. The redistribution circuit has a plurality of bump pads and a plurality of line pads thereon. The second chip has an active surface with a plurality of second bonding pads thereon. Bumps are positioned between the bump contacts and the first bonding pads and between the bump pads and the second bonding pads. Conductive wires connect the line contacts and the line pads. The underfill material fills the space between the chip and the substrate and the gap between the first and the second chips.