Abstract: According to embodiments of the present invention, a method of additive manufacturing of an object using object material is provided. The method includes forming the object by processing some of the object material, and forming an object identifier by forming a pattern having at least one coded volume within an internal volume of the object, each of the at least one coded volume enclosing unprocessed object material. According to further embodiments of the present invention, an object manufactured using the method of additive manufacturing and a method of scanning an object identifier formed using the method of additive manufacturing are is also provided.

Abstract: In one example, a printhead having an electrically-functional optical target. The printhead includes a substrate. An optical target having an optically-distinguishable shape and formed from at least one polysilicon strip is deposited on the substrate. An electrical connection to at least one of the polysilicon strips connect the strip into a circuit that is deposited on the substrate.

Abstract: In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.

Abstract: In one example, a printhead having an electrically-functional optical target. The printhead includes a substrate. An optical target having an optically-distinguishable shape and formed from at least one polysilicon strip is deposited on the substrate. An electrical connection to at least one of the polysilicon strips connect the strip into a circuit that is deposited on the substrate.

Abstract: Ink property sensing on a printhead is described. In an example, a substrate for a printhead includes a cap layer having bores. Chambers are formed beneath the cap layer in fluidic communication with the bores. Fluid ejectors are disposed in at least a portion of the chambers. At least one ion-sensitive field effect transistor (ISFET) is disposed in a respective at least one of the chambers. An electrode is disposed in each of the chambers having an ISFET and capacitively coupled to said ISFET through a dielectric.

Abstract: In one example in accordance with the present disclosure a printhead with a number of EPROM cells is described. The printhead deposits fluid onto a print medium. The printhead also includes a number of EPROM cells. Each EPROM cell includes a substrate having a source and a drain disposed therein, a floating gate separated from the substrate by a first dielectric layer. The floating gate includes a multi-metal layer that is a metal etched layer. Each EPROM cell also includes a control gate separated from the multi-metal layer of the floating gate by a second dielectric layer.

Abstract: In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.

Abstract: A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel region situated between a drain region and a source region. The first dielectric layer is situated over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The second dielectric layer is situated over the floating gate and the control gate is capacitively coupled to the floating gate through the second dielectric layer. A dielectric nitride layer is situated between the floating gate and the second dielectric layer to prevent charge loss from the floating gate to the second dielectric layer.

Abstract: Ink property sensing on a printhead is described. In an example, a substrate for a printhead includes a cap layer having bores. Chambers are formed beneath the cap layer in fluidic communication with the bores. Fluid ejectors are disposed in at least a portion of the chambers. At least one ion-sensitive field effect transistor (ISFET) is disposed in a respective at least one of the chambers. An electrode is disposed in each of the chambers having an ISFET and capacitively coupled to said ISFET through a dielectric.

Abstract: A resistive memory element is provided, having a bottom electrode, a top electrode, and an active region sandwiched therebetween. The resistance memory element has a V-shape. Methods of manufacturing the V-shape resistive memory element and crossbar structures employing the V-shape resistive memory element are also provided.

Abstract: Examples of fluid ejection apparatuses and methods for making fluid ejection apparatuses are described. An example method may include forming a fluid feed slot in a bulk layer of a substrate, forming a plurality of ink feed channels in at least an epitaxial layer of the substrate, each of the ink feed channels fluidically coupled to the fluid feed slot, and forming a plurality of drop generators over the substrate such that the epitaxial layer of the substrate is between the plurality of drop generators and the bulk layer and such that the each of the drop generators is fluidically coupled to the fluid feed slot by at least one of the ink feed channels.

Abstract: Examples of fluid ejection apparatuses and methods for making fluid ejection apparatuses are described. An example method may include forming a fluid feed slot in a bulk layer of a substrate, forming a plurality of ink feed channels in at least an epitaxial layer of the substrate, each of the ink feed channels fluidically coupled to the fluid feed slot, and forming a plurality of drop generators over the substrate such that the epitaxial layer of the substrate is between the plurality of drop generators and the bulk layer and such that the each of the drop generators is fluidically coupled to the fluid feed slot by at least one of the ink feed channels.

Abstract: A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area.

Abstract: An example provides an apparatus including a plate having a nozzle orifice, a flat portion, and a first surface having a recess forming a corresponding protrusion extending from a second surface, opposite first surface, of the plate. A substrate may be in spaced relation to the flat portion of the plate such that the protrusion extends toward the substrate and such that the flat portion and the substrate define, at least in part, a chamber.

Abstract: A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel region situated between a drain region and a source region. The first dielectric layer is situated over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The second dielectric layer is situated over the floating gate and the control gate is capacitively coupled to the floating gate through the second dielectric layer. A dielectric nitride layer is situated between the floating gate and the second dielectric layer to prevent charge loss from the floating gate to the second dielectric layer.

Abstract: An example provides an apparatus including a plate having a nozzle orifice, a flat portion, and a first surface having a recess forming a corresponding protrusion extending from a second surface, opposite first surface, of the plate. A substrate may be in spaced relation to the flat portion of the plate such that the protrusion extends toward the substrate and such that the flat portion and the substrate define, at least in part, a chamber.

Abstract: A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area.

Abstract: An intra-metal capacitor unit cell comprises a first electrode and a second electrode formed in the same device layer. A dielectric layer separates the electrodes. The first electrode is substantially surrounded by the second electrode. Misalignment between the first and second electrodes does not substantively alter the capacitance of the unit cell.

Abstract: A structure and method of fabrication of a capacitor and other devices by providing a semiconductor structure and providing a top insulating layer and conductive features over the semiconductor structure; forming a first conductive layer over the top insulating layer; patterning the first conductive layer to form at least a capacitor bottom plate and a first portion of the first conductive layer; forming a capacitor dielectric layer over the top insulating layer and the capacitor bottom plate and the first portion of the first conductive layer; forming a second conductive layer over the capacitor dielectric layer; and patterning the second conductive layer to form at least a top plate over the bottom plate and a first section of the second conductive layer on the capacitor dielectric layer. The embodiment can further comprise conductive features in the top insulating layer that can underlie the bottom plate, the first portion or/and the first section.

Abstract: An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing.