Patents by Inventor Chayathorn Saklang
Chayathorn Saklang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250210479Abstract: A self-powered microelectronic semiconductor device includes low temperature interconnection and encapsulation materials to enable integration of a battery with the microelectronics package during manufacture. The package includes a partially exposed leadframe or leads of a substrate for connecting the battery. The battery includes one or more terminal connectors that can either be manufactured by the battery vendor or externally attached using spot/laser or resistance welding. The steps of connecting the battery to the package are performed after the microelectronic package assembly to ensure the battery does not experience any high temperatures from the package assembly process. Cavities are formed in an overmolded molding compound to expose the leadframe or battery pads for electronic connection. A low temperature electrically conductive bonding agent is used to create the electrical and mechanical bond of the battery tabs to the leadframe.Type: ApplicationFiled: December 20, 2023Publication date: June 26, 2025Inventors: Namrata Kanth, Stephen Ryan Hooper, Chayathorn Saklang, Michael B. Vincent, Matthew Wayne Muddiman
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Publication number: 20250085182Abstract: One or more sensor devices are encapsulated on a top surface of a carrier substrate within an elastomer material. The carrier substrate includes one or more recessed channels adjacent to each sensor device which are filled by a portion of the elastomer material to create flanged areas that are level with the top surface of the carrier substrate. A cover which can include a liquid or gas input port or other related structures can be placed over each sensor device and bonded to the carrier substrate at the flanged areas, creating a seal between the cover and the carrier substrate that surrounds each sensor device.Type: ApplicationFiled: September 11, 2023Publication date: March 13, 2025Inventors: Chayathorn Saklang, Stephen Ryan Hooper, Julien Juéry
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Publication number: 20250079335Abstract: Vibration isolation can be provided for a vibration sensitive component to be bonded to electronic circuit boards or other surfaces by an assembly that includes two substrates with rigid portions that are electrically coupled to each other via a flexible interconnect. The rigid portions of the two substrates are bonded together via an elastic structure in a stacked arrangement with the first substrate above the second substrate. The flexible interconnect electrically couples the first substrate to the second substrate and the second substrate is configured to be bonded and electrically coupled to an electronic circuit board or other larger substrate via contacts on a surface of the rigid portion of the second substrate. The vibration sensitive component can be bonded to the rigid portion of the first substrate and couped to the flexible interconnect via the first substrate, thereby coupling it to the second substrate and the larger substrate.Type: ApplicationFiled: August 30, 2023Publication date: March 6, 2025Inventors: Michael B. Vincent, Stephen Ryan Hooper, Scott M. Hayes, Dwight Lee Daniels, Chayathorn Saklang
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Publication number: 20240425364Abstract: Alignment features formed on a cover substrate allow for a second substrate to be bonded to the cover substrate while ensuring that the second substrate is not titled with respect to a plane defined by the alignment features. Die attachment material is patterned such that it deforms or flows underneath the second substrate while allowing corners of the second substrate to rest on landing areas that are elevated above the top surface of the cover substrate. Some of the landing areas may include additional features that are elevated above the landing areas to form notches which constrain the rotational position of the second in addition to its tilt.Type: ApplicationFiled: June 20, 2023Publication date: December 26, 2024Inventors: Chayathorn Saklang, Stephen Ryan Hooper, Dwight Lee Daniels, Scott M Hayes, Jin Yang
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Publication number: 20240425367Abstract: An alignment recess formed in a cover substrate such as a cover for a MEMS device allows a second substrate to be bonded to the cover substrate. The alignment recess is larger than the second substrate and has two corner regions diagonally opposite each other where a wall of the recess protrudes to form a notch. The notch is dimensioned such that when the second substrate is disposed within the recess with two opposing corners surrounded by respective notches of the recess, the angular position of the second substrate relative to the cover substrate can be controlled to within a desired amount of rotation.Type: ApplicationFiled: June 20, 2023Publication date: December 26, 2024Inventors: Chayathorn Saklang, Stephen Ryan Hooper, Scott M Hayes, Dwight Lee Daniels, Jin Yang
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Patent number: 12125771Abstract: A semiconductor package comprises a leadframe, a component module, and a semiconductor die. The leadframe has a plurality of insertion terminals, a split die pad, and one or more leads. The component module has one or more passive components mounted on a substrate. The semiconductor die has an integrated circuit. The component module is mounted on a split die pad at a first surface of the leadframe and forms an electrical connection with the insertion terminals. Further, the semiconductor die is mounted on the split die pad at a second surface of the leadframe which is opposite to the first surface.Type: GrantFiled: December 8, 2021Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: Chayathorn Saklang, Chanon Suwankasab, Amornthep Saiyajitara, Verapath Vareesantichai
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Publication number: 20240332105Abstract: A multidevice package includes upper and lower surfaces with the lower surface disposed beneath a first die forming part of the package. The lower surface includes a first a set of electrical contacts and a recessed region with a second set of electrical contacts configured to allow a second die to be coupled to the lower surface and electrically coupled to the first die via the second set of contacts. The recessed region is sufficiently recessed to allow the package to be coupled to a mounting surface such as a printed circuit board via the first set of contacts while the second die remains suspended above the mounting surface.Type: ApplicationFiled: April 3, 2023Publication date: October 3, 2024Inventors: Namrata Kanth, Scott M. Hayes, Stephen Ryan Hooper, Chayathorn Saklang, Burton Jesse Carpenter
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Publication number: 20240178111Abstract: A method of manufacturing a semiconductor device with an attached battery is provided. The method includes affixing a semiconductor die to a die pad region of a first battery lead of a leadframe. The first battery lead of the leadframe is separated from a second battery lead of the leadframe. An encapsulant encapsulates the semiconductor die and portions of the first and second battery leads of the leadframe. The battery is affixed to an exposed portion of the first battery lead of the leadframe such that a first terminal of the battery is conductively connected to the first battery lead. An exposed portion of the second battery lead of the leadframe is bent to overlap a top surface portion of the battery such that a second terminal of the battery conductively connected to the second battery lead.Type: ApplicationFiled: November 29, 2022Publication date: May 30, 2024Inventors: Chayathorn Saklang, Namrata Kanth, Stephen Ryan Hooper, Scott M. Hayes
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Publication number: 20230343683Abstract: A method of manufacturing a packaged semiconductor device is provided. The method includes affixing a sensor system to a die pad portion of a leadframe. A battery is affixed to the lead frame including a first terminal of the battery affixed to a first leg of the leadframe and a second terminal of the battery affixed to a second leg of the leadframe. An encapsulant encapsulates the sensor system, battery, and leadframe.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Inventors: Stephen Ryan Hooper, Chanon Suwankasab, Chayathorn Saklang, Crispulo Estira Lictao, JR., Amornthep Saiyajitara, Dominic (PohMeng) Koey
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Publication number: 20230178457Abstract: A semiconductor package comprises a leadframe, a component module, and a semiconductor die. The leadframe has a plurality of insertion terminals, a split die pad, and one or more leads. The component module has one or more passive components mounted on a substrate. The semiconductor die has an integrated circuit. The component module is mounted on a split die pad at a first surface of the leadframe and forms an electrical connection with the insertion terminals. Further, the semiconductor die is mounted on the split die pad at a second surface of the leadframe which is opposite to the first surface.Type: ApplicationFiled: December 8, 2021Publication date: June 8, 2023Inventors: Chayathorn Saklang, Chanon Suwankasab, Amornthep Saiyajitara, Verapath Vareesantichai
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Patent number: 11482478Abstract: An electronic device package includes a first die coupled to a substrate, a second die coupled with the first die, and a spacer element coupled to the second die to form a stacked structure that includes the first die, the second die, and the spacer element. An electrically conductive shield overlies the stacked structure. The shield has a first end coupled to the spacer element and a second end coupled to the substrate. Inter-chip bond wires may electrically interconnect the first and second dies, and the shield may additionally overlie the bond wires. The spacer element may extend above a surface of the second die at a height that is sufficient to prevent the shield from touching the inter-chip bond wires.Type: GrantFiled: July 23, 2020Date of Patent: October 25, 2022Assignee: NXP B.V.Inventors: Crispulo Estira Lictao, Jr., Chayathorn Saklang, Amornthep Saiyajitara, Chanon Suwankasab, Stephen Ryan Hooper, Bernd Offermann
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Publication number: 20220028766Abstract: An electronic device package includes a first die coupled to a substrate, a second die coupled with the first die, and a spacer element coupled to the second die to form a stacked structure that includes the first die, the second die, and the spacer element. An electrically conductive shield overlies the stacked structure. The shield has a first end coupled to the spacer element and a second end coupled to the substrate. Inter-chip bond wires may electrically interconnect the first and second dies, and the shield may additionally overlie the bond wires. The spacer element may extend above a surface of the second die at a height that is sufficient to prevent the shield from touching the inter-chip bond wires.Type: ApplicationFiled: July 23, 2020Publication date: January 27, 2022Inventors: Crispulo Estira Lictao, JR., Chayathorn Saklang, Amornthep Saiyajitara, Chanon Suwankasab, Stephen Ryan Hooper, Bernd Offermann
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Patent number: 11114239Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.Type: GrantFiled: November 20, 2019Date of Patent: September 7, 2021Assignee: NXP B.V.Inventors: Chayathorn Saklang, Wiwat Tanwongwan, Amornthep Saiyajitara, Chanon Suwankasab
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Patent number: 11049817Abstract: A shielded semiconductor device has a first die attached to a die pad of a lead frame and a second die attached to a surface of the first die. The first die is electrically connected to inner lead ends of leads that surround the die pad, and the second die is electrically connected to the first die and to an inner end of a shielding lead. A mold compound forms a body around the first and second dies and the electrical connections. Outer lead ends of the leads project from the sides of the body. The outer end of the shielding lead projects from a central location of one side of the body and is bent up the side surface from which it projects and over the top of the body and provides EMI shielding.Type: GrantFiled: February 25, 2019Date of Patent: June 29, 2021Assignee: NXP B.V.Inventors: Chayathorn Saklang, Amornthep Saiyajitara, Chanon Suwankasab, Russell Joseph Lynch
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Publication number: 20210151251Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.Type: ApplicationFiled: November 20, 2019Publication date: May 20, 2021Inventors: Chayathorn Saklang, Wiwat Tanwongwan, Amornthep Saiyajitara, Chanon Suwankasab
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Patent number: 10790220Abstract: A press-fit semiconductor device includes a lead frame having a die pad, leads with inner and outer lead ends, and a press-fit lead. The press-fit lead has a circular section between an outer lead end and an inner lead end, and the circular section has a central hole that is sized and shaped to receive a press-fit connection pin. A die is attached to the die pad and electrically connected to the inner lead ends of the leads and the inner lead end of the press-fit lead. The die, electrical connections and inner lead ends are covered with an encapsulant that forms a housing. The outer lead ends of the leads extend beyond the housing. The housing has a hole extending therethrough that is aligned with the center hole of the press-fit lead, so that a press-fit connection pin can be pushed through the hole to connect the device to a circuit board.Type: GrantFiled: October 18, 2018Date of Patent: September 29, 2020Assignee: NXP B.V.Inventors: Chayathorn Saklang, Stephen Ryan Hooper, Chanon Suwankasab, Amornthep Saiyajitara, Bernd Offermann, James Lee Grothe, Russell Joseph Lynch
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Publication number: 20200273810Abstract: A shielded semiconductor device has a first die attached to a die pad of a lead frame and a second die attached to a surface of the first die. The first die is electrically connected to inner lead ends of leads that surround the die pad, and the second die is electrically connected to the first die and to an inner end of a shielding lead. A mold compound forms a body around the first and second dies and the electrical connections. Outer lead ends of the leads project from the sides of the body. The outer end of the shielding lead projects from a central location of one side of the body and is bent up the side surface from which it projects and over the top of the body and provides EMI shielding.Type: ApplicationFiled: February 25, 2019Publication date: August 27, 2020Inventors: Chayathorn Saklang, Amomthep Saiyaitara, Chanon Suwankasab, Russell Joseph Lynch
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Publication number: 20200126895Abstract: A press-fit semiconductor device includes a lead frame having a die pad, leads with inner and outer lead ends, and a press-fit lead. The press-fit lead has a circular section between an outer lead end and an inner lead end, and the circular section has a central hole that is sized and shaped to receive a press-fit connection pin. A die is attached to the die pad and electrically connected to the inner lead ends of the leads and the inner lead end of the press-fit lead. The die, electrical connections and inner lead ends are covered with an encapsulant that forms a housing. The outer lead ends of the leads extend beyond the housing. The housing has a hole extending therethrough that is aligned with the center hole of the press-fit lead, so that a press-fit connection pin can be pushed through the hole to connect the device to a circuit board.Type: ApplicationFiled: October 18, 2018Publication date: April 23, 2020Inventors: Chayathorn Saklang, Stephen Ryan Hooper, Chanon Suwankasab, Amornthep Saiyajitara, Bernd Offermann, James Lee Grothe, Russell Joseph Lynch
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Patent number: 10340211Abstract: A sensor module, such as an acceleration sensor module, includes a leaded socket assembly covered by a housing. The leaded socket assembly includes a dual gauge lead frame, a sensor die, and various passive devices. The sensor die and the passive devices are mounted on the lead frame, and then the lead frame, sensor die, and passive devices are over-molded to form the leaded socket assembly. Neither the sensor module nor the socket assembly includes a printed circuit board, so many conventional sensor module assembly steps are bypassed.Type: GrantFiled: March 15, 2018Date of Patent: July 2, 2019Assignee: NXP B.V.Inventors: Chanon Suwankasab, Amornthep Saiyajitara, Chayathorn Saklang, Stephen Ryan Hooper
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Patent number: 9824980Abstract: Various aspects are directed to apparatuses, systems and related methods involving the mitigation of issues relating to thermal expansion and contraction of lead fingers of an integrated circuit package. Consistent with one or more embodiments, lead fingers on a leadframe substrate each have a locking structure that secures the lead finger in place relative to the substrate. The lead fingers provide a location to attach a bond wire to an integrated circuit, and connect the bond wire to terminals at a perimeter of the leadframe. The locking structure and arrangement of the lead fingers mitigate issues such as cracking or breaking of a solder connection of the bond wire to the leadframe, which can occur due to thermal expansion and contraction.Type: GrantFiled: June 27, 2014Date of Patent: November 21, 2017Assignee: NXP B.V.Inventors: Chayathorn Saklang, Wiwat Tanwongwan