Abstract: Provided are a visual interface display method and apparatus, an electronic device, and a storage medium. The display method includes determining that a target vehicle executes a driving task (S101); displaying a map within a preset range according to the real-time position of the target vehicle (S102); displaying a first object model for a first object detected by the target vehicle on the map; and displaying a second object model including at least point cloud data for a detected non-first object (S103).

Abstract: An electronic package is provided, in which a surface treatment layer is formed on parts of a surface of a functional pad, such that an electronic element is in contact with and bonded to the functional pad and the surface treatment layer via a bonding layer. Therefore, when the electronic package undergoes thermal shock, the surface treatment layer having buffering capability can improve packaging reliability of the electronic package.

Abstract: A display device includes a screen, a screen stand and a fixing module. The screen stand is pivotally connected to the screen. The fixing module is connected to the screen stand and configured to clamp a first surface and a second surface of a board and includes a connecting element, a first abutting element and a second abutting element. The first abutting element is fixed to the connecting element and configured to abut against the first surface of the board. The second abutting element is pivotally connected to the connecting element and includes an abutting end configured to abut against the second surface of the board.

Abstract: A voltage measurement device for pulse-width modulation (PWM) signals is provided, which includes a conversion circuit and a processing circuit. The conversion circuit receives a first PWM signal and a second PWM signal from a motor driving device, and converts the first PWM signal and the second PWM signal into the absolute value signal and the polarity signal of the line-to-line voltage signal between the first PWM signal and the second PWM signal. The processing circuit converts the polarity signal and the absolute value signal into a first integral signal and a second integral signal, and reconstructs the line-to-line voltage signal according to the first integral signal and the second integral signal so as to obtain the reconstructed voltage signal of the line-to-line voltage signal.

Abstract: A manufacturing method of an interconnect structure including the following is provided. A substrate is provided. Sacrificial layers are formed on the substrate. A dielectric layer is formed between two adjacent sacrificial layers. There is an air gap in the dielectric layer. The sacrificial layers are removed to form first openings. A conductive layer is formed in the first opening.

Abstract: An apparatus including a semiconductor substrate; an absorption layer coupled to the semiconductor substrate, the absorption layer including a photodiode region configured to absorb photons and to generate photo-carriers from the absorbed photons; one or more first switches controlled by a first control signal, the one or more first switches configured to collect at least a portion of the photo-carriers based on the first control signal; and one or more second switches controlled by a second control signal, the one or more second switches configured to collect at least a portion of the photo-carriers based on the second control signal, where the second control signal is different from the first control signal.

Abstract: The present application discloses a method, system, and computer system for detecting malicious files. The method includes receiving a sample, extracting an embedded script from the sample, applying a malicious script detector in connection with determining whether the sample is malicious, and in response to determining that the sample is malicious sending, to a security entity, an indication that the sample is malicious.

Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.

Abstract: A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

Abstract: A method for making a foam component is provided and includes inserting a foam material into a cavity of a mold having a top plate and a bottom plate, heating the foam material to cause the foam material to expand, and moving one of the top plate and the bottom plate relative to the other of the top plate and the bottom plate as the foam material expands and contacts the one of the top plate and the bottom plate to cause the foam material to fold over on itself within the cavity.

Abstract: A connector assembly includes a metal shielding cage. The metal shielding cage includes a cage body, a back cover and a grounding member. The cage body has a top wall, a mounting side and two side walls, the top wall, the mounting side and the two side walls together define a receiving space extending along a front-rear direction, the receiving space has a front opening toward the front and a rear opening positioned at the rear, the back cover and the grounding member are assembled at the rear opening of the cage body, and the grounding member is provided with an elastic grounding finger row toward the mounting side.

Abstract: A connector assembly includes a guide shielding cage, an internal biasing heat sink and two lateral heat dissipating members. The guide shielding cage includes a cage body and a partitioning bracket provided in the cage body, the cage body has a top wall and two side walls, the partitioning bracket has an upper wall and a lower wall which together define an interior receiving space, and the partitioning bracket and the cage body together define an upper receiving space and a lower receiving space, each side wall of the cage body is formed with a side window which is communicated with the interior receiving space, the lower wall of the partitioning bracket is formed with a lower window which allows the interior receiving space to be communicated with the lower receiving space. The internal biasing heat sink is provided in the partitioning bracket and has an internal heat dissipating member, the internal heat dissipating member enters into the lower receiving space via the lower window.

Abstract: Immunogenic compositions comprising partially glycosylated viral glycoproteins for use as vaccines against viruses are provided. Vaccines formulated using mono-, di-, or tri-glycosylated viral surface glycoproteins and polypeptides provide potent and broad protection against viruses, even across strains. Pharmaceutical compositions comprising monoglycosylated hemagglutinin polypeptides and vaccines generated therefrom and methods of their use for prophylaxis or treatment of viral infections are disclosed. Methods and compositions are disclosed for influenza virus HA, NA and M2, RSV proteins F, G and SH, Dengue virus glycoproteins M or E, hepatitis C virus glycoprotein E1 or E2 and HIV glycoproteins gp120 and gp41.

Abstract: The invention introduces an apparatus for handling flash physical-resource sets, at least including a random access memory (RAM), a processing unit and an address conversion circuit. The RAM includes multiple segments of temporary space and each segment thereof stores variables associated with a specific flash physical-resource set. The processing unit accesses user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL). The address conversion circuit receives a memory address issued from the FTL, converts the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and outputs the relative address to the RAM for accessing a variable of the associated segment of temporary space.

Abstract: A radio apparatus and system may include a means for modulating and/or demodulating an optical signal for respective transmission and/or reception of the optical signal using an optical channel connected to a remote radio unit. There may also be provided a means for performing, based on one or more pre-trained computational models, one or more operations on a digital signal corresponding to the optical signal for mitigating one or more non-linearities introduced by the optical modulating and/or demodulating means and the optical channel. The one or more pre-trained computational models may be pre-trained based on feedback data indicative of said one or more non-linearities.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Abstract: A patterning method includes the following steps. A mask layer is formed on a material layer. A first hole is formed in the mask layer by a first photolithography process. A first mask pattern is formed in the first hole. A second hole is formed in the mask layer by a second photolithography process. A first spacer is formed on an inner wall of the second hole. A second mask pattern is formed in the second hole after the step of forming the first spacer. The first spacer surrounds the second mask pattern in the second hole. The mask layer and the first spacer are removed. The pattern of the first mask pattern and the second mask pattern are transferred to the material layer by an etching process.

Abstract: A pressure sensing unit, a capacitive hybrid sensor device, and an input apparatus using the same are provided. The pressure sensing unit for detecting pressing events includes a pressure sensing pad group and a floating conductive element. The pressure sensing pad group includes a first pressure sensing pad, a second pressure sensing pad, and a ground pad that are spaced apart from one another. The first and second pressure sensing pads are electrically shielded from each other by the ground pad. One among the floating conductive element and the pressure sensing pad group is configured to be movable in a movement direction relative to another one among the floating conductive element and the pressure sensing pad group. The floating conductive element overlaps with the pressure sensing pad group in the movement direction. Therefore, a signal-to-noise ratio can be increased and an erroneous detection can be prevented.

Abstract: An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.

Abstract: The present application discloses method for fabricating a semiconductor device. The method includes providing a substrate; forming a word line trench in the substrate; conformally forming a first insulating layer in the word line trench and conformity forming a first barrier layer on the first insulating layer; conformally forming a first nucleation layer on the first barrier layer; performing a post-treatment to the first nucleation layer, wherein the post-treatment comprises a reducing agent comprising diborane and a tungsten-containing precursor; forming a first bulk layer on the first nucleation layer, wherein the first nucleation layer and the first bulk layer configure a first conductive layer; and performing a planarization process to turn the first insulating layer, the first barrier layer, and the first conductive layer into a word line insulating layer, a word line barrier layer, and a word line conductive layer, respectively and correspondingly.