Abstract: A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact opening to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.

Abstract: A novel design for an electrically erasable and programmable read only memory device is described. Particular features of the design include a floating gate that is partly located beneath the surface and and an efficient electron emitter to facilitate electron transfer between floating and control gates. The method for constructing the device is disclosed in detail.

Abstract: A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact openings to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.