Abstract: A semiconductor includes a first substrate having a device region and a ring region surrounding the device region, a first interconnect structure over the first substrate, the first interconnect structure including a first via tower and a second via tower, a first bonding layer over the first interconnect structure and including a first metal bonding feature, a second bonding layer over the first bonding layer and including a second metal bonding feature in contact with the first metal bonding feature, and a second interconnect structure over the second bonding layer and including a third via tower extending through the second interconnect structure and disposed directly over the ring region. The first via tower is electrically coupled to the second via tower by a first metal line. The first via tower is electrically coupled to the third via tower by the first metal bonding feature and the second metal bonding feature.

Abstract: An electronic device including a display panel and a CPU is provided. The display panel updates displayed images at a refresh rate. The CPU implements a latency monitor, a system resource controller, a display controller, and an application. The latency monitor collects time information related to touch latency. The touch latency is the duration between the time point at which the display panel detects a touch event and the time point at which the display panel displays an image generated by the application in response to said touch event. The display controller informs the system resource controller of the refresh rate. The system resource controller adjusts the resource allocation of the electronic device to cause the touch latency to be lower than a threshold, according to the time information and the refresh rate.

Abstract: An acoustic wave device includes a piezoelectric substrate and a transducer. The piezoelectric substrate has a surface. The transducer is disposed on the surface. The transducer includes a first electrode, a second electrode, and at least one protrusion. The first electrode extends along a first direction and has a first end. The second electrode extends along the first direction and has a second end. The first electrode and the second electrode are spaced apart from each other along a second direction. The at least one protrusion is disposed at the first end of the first electrode. The at least one protrusion extends along the first direction and partially obstruct the first end.

Abstract: A method for adjusting application settings is provided. The method includes using an application setting module to receive at least one performance target from an application running on an electronic device. The method further includes using the application setting module to record at least one performance indicator of the application while the application is running, wherein the performance indicator corresponds to the performance target. The method further includes using the application setting module to estimate the estimated time that the temperature of the electronic device sustains less than the defense temperature. The method further includes using the application setting module to determine the score according to the performance indicator and the estimated time, wherein the score indicates to the application that it should raise, lower, or keep a current setting.

Abstract: A transmission channel switching method is provided. The transmission channel switching method may include the following steps. An apparatus may establish a plurality of transmission channels. The apparatus may transmit data through a default transmission channel of the transmission channels, wherein the default transmission channel corresponds to the lowest power consumption. The apparatus may determine whether to switch to another transmission channel of the transmission channels according to channel quality of each transmission channel and power consumption corresponds to each transmission channel.

Abstract: An electronic device includes a processor arranged to execute an application, a platform and a middleware. The application is configured to execute operations of: providing at least one acceptable quality and at least one priority of the at least one profile parameter. The platform is configured to execute an operation of: providing platform information in response to a demand request. The middleware is configured to execute operations of: receiving the at least one acceptable quality and the at least one priority from the application; receiving the platform information from the platform; performing a self-adaptive algorithm according to the platform information to generate a result; adjusting the at least one profile parameter according to the result, the at least one acceptable quality and the at least one priority; and transmitting an adjustment notification to the platform, after adjusting the at least one profile parameter.

Abstract: A method of forming a semiconductor structure, includes forming a fin structure over a substrate in a Z-direction; forming a dummy gate structure extending in a Y-direction and over the fin structure; and forming gate spacers on sidewalls of the dummy gate structure. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes removing a portion of the dummy gate structure to form a first trench that exposes upper portions of the gate spacers; forming an insulating material in the first trench; partially removing the insulating material to form insulating layers on sidewalls of the upper portions of the gate spacers; removing a remaining portion of the dummy gate structure to expose lower portions of the gate spacers; and partially etching the lower portions of the gate spacers.

Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.

Abstract: A method of testing a semiconductor package includes: forming a charge measurement unit over a carrier substrate; forming a first dielectric layer over the charge measurement unit; forming a first metallization layer over the dielectric layer, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer.

Abstract: An electronic device is provided. The electronic device includes a first substrate; a second substrate disposed opposite to the first substrate; a liquid crystal layer disposed between the first substrate and the second substrate; a plurality of first electrodes disposed between the first substrate and the liquid crystal layer; a plurality of second electrodes disposed between the second substrate and the liquid crystal layer; a first signal line disposed between the first substrate and the liquid crystal layer, and electrically connected to one of the plurality of first electrodes; and a second signal line disposed between the second substrate and the liquid crystal layer, and electrically connected to one of the plurality of second electrodes. The first signal line and the second signal line include a blackened metal.

Abstract: A device resource provisioning method is provided. The method leverages intra-frame information to optimize device resource utilization. The method involves obtaining intra-frame information of the current frame from a running application during rendering the current frame, and adjusting the device resources provided to the running application dynamically based on the intra-frame information of the current frame.

Abstract: An electronic device is provided. The electronic device includes a display panel and a controller coupled to the display panel. The display panel is configured to update displayed images at a refresh rate. The controller is configured to receive a target frame rate from a first application. The controller is further configured to determine a frame rate according to the refresh rate and the target frame rate. The frame rate is a factor of the refresh rate. The controller is further configured to control the first application to draw images at the frame rate.

Abstract: A method for dynamic adaptive threading is provided. The method comprises receiving a query request for a recommended number of threads from an application. The method comprises determining the recommended number of threads according to a resource status of a system-on-a-chip (SoC) platform. The method comprises transmitting the recommended number of threads to the application.

Abstract: A method for adaptive multi-window technology includes detecting a multi-window scenario corresponding to a plurality of windows on an electronic device, determining priorities of the plurality of windows, monitoring a plurality of performance indexes of the electronic device, checking whether resource re-allocation is needed according to the performance indexes, determining targets of the plurality of windows if resource re-allocation is needed, and changing profiles of the targets according to a resource re-allocation algorithm.

Abstract: An integrated circuit (IC) package includes a first integrated circuit (IC) device. An interconnection structure is disposed over the first IC device in a cross-sectional side view. The interconnection structure includes a plurality of interconnection components. A cavity is disposed in the interconnection structure in the cross-sectional side view. A second IC device is disposed at least partially within the cavity in the cross-sectional side view. The second IC device is electrically coupled to the first IC device through at least a subset of the interconnection components of the interconnection structure. A non-metallic material partially fills the cavity. The second IC device is at least partially surrounded by the non-metallic material in the cross-sectional side view and in a top view.

Abstract: A semiconductor structure includes an interconnect structure, a passivation structure, a first capacitor, and a contact feature. The interconnect structure is disposed over a semiconductor substrate. The passivation structure is disposed over the interconnect structure. The first capacitor is disposed within the passivation structure. The contact feature is disposed over the passivation structure, wherein the first capacitor is proximal to a corner of the contact feature. A method of manufacturing the semiconductor structure is also provided.

Abstract: A method for enhancing resolution of a radiation sensitive microcapsule-based printer includes generating multiple subpixels in a sub-scan direction. The method further includes mapping multiple grids onto a photosensitive medium, the multiple grids corresponding to the multiple subpixels. The method further includes determining an exposure energy required for each grid of the multiple grids. The method further includes allocating the exposure energy required for each grid into a first exposure level and a second exposure level. The method further includes exposing each grid of the photosensitive medium to the corresponding first exposure level and the corresponding second exposure level sequentially as the photosensitive medium passes through the radiation sensitive microcapsule-based printer in the sub-scan direction.

Abstract: A semiconductor structure includes a first die; a molding surrounding the first die; a redistribution layer (RDL) disposed under the first die and the molding, and including a plurality of first conductive pads and a dielectric layer surrounding the plurality of first conductive pads; a second die disposed under the RDL, and including a plurality of first die pads over the second die; and a plurality of first conductive bumps disposed between the RDL and the second die, wherein each of the plurality of first conductive bumps is electrically coupled with corresponding one of the plurality of first die pads and corresponding one of the plurality of first conductive pads, the plurality of first die pads are respectively arranged at corners of the second die, and the plurality of first conductive bumps are electrically connected in series.

Abstract: The invention provides a semiconductor structure, which comprises a middle/high voltage device region and a low voltage device region, a plurality of fin structures disposed in the low voltage device region, and a protruding part located at a boundary Between the middle/high voltage device region and the low voltage device region. A top surface of the protruding part is flat, and the top surface of the protruding part is aligned with a flat top surface of the middle/high voltage device region.

Abstract: A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a gate electrode layer formed over a semiconductor substrate and capped with a conductive capping layer. The semiconductor device structure also includes an insulating capping stack having a lower surface that faces and is spaced apart from an upper surface of the conductive capping layer. In addition, the semiconductor device structure includes gate spacers formed over the semiconductor substrate and covering opposing sidewalls of the gate electrode layer, the conductive capping layer, and the insulating capping stack.