Patents by Inventor Che-Cheng Chang

Che-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for semiconductor device fabrication with improved source drain proximity
    Patent number: 10748912
    Abstract: A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Han Lin, Che-Cheng Chang, Horng-Huei Tseng
  • SEMICONDUCTOR DEVICE
    Publication number: 20200243520
    Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Fin-type field effect transistor structure and manufacturing method thereof
    Patent number: 10727227
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Via structure and methods thereof
    Patent number: 10727178
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Fin field effect transistor, semiconductor device and method for fabricating the same
    Patent number: 10727132
    Abstract: A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until gaps are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Semiconductor Structure and Manufacturing Method Thereof
    Publication number: 20200235095
    Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
  • Metal gate process for FinFET device improvement
    Patent number: 10714588
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Semiconductor device and manufacturing method thereof
    Patent number: 10714581
    Abstract: A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Fin Field Effect Transistor (FINFET) Device and Method for Forming the Same
    Publication number: 20200220019
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.
    Type: Application
    Filed: March 18, 2020
    Publication date: July 9, 2020
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Yung-Jung Chang
  • Image positioning method and image positioning device for using the same
    Patent number: 10704917
    Abstract: An image positioning method and an image positioning device for using the same is disclosed. The method finds the position of a vehicle that is driving on a road, and a plurality of signs is arranged on the road. Firstly, an electronic map having a plurality of paths, a plurality reference images, and characteristic positions of the plurality of paths and the plurality reference images is provided. Next, at least two positioning images of the signs closest to the vehicle are sequentially retrieved. The reference image identical to the positioning images are searched on the electronic map and used as characteristic images. When the order of all the characteristic images corresponds to the order of all the positioning images, the position of the vehicle is estimated according to the path corresponding to all the characteristic images and the characteristic positions of all the characteristic images.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 7, 2020
    Assignee: AUTOMOTIVE RESEARCH & TESTING CENTER
    Inventors: Che-Cheng Chang, Yi Yan, Wun-Sheng Yao
  • Semiconductor device and methods of manufacture
    Patent number: 10700208
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10700180
    Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, a first gate spacer, an interlayer dielectric layer, a contact stop layer, and an air gap. The gate structure is disposed over the semiconductor substrate. The first gate spacer covers a first sidewall of the gate structure. The interlayer dielectric layer is adjacent to the first gate spacer. The contact stop layer is positioned over the first gate spacer and the interlayer dielectric layer. The air gap is between the first gate spacer and the interlayer dielectric layer. The contact stop layer includes a capping portion that seals a top of the air gap.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Dry etching apparatus
    Patent number: 10692701
    Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Tung-Wen Cheng, Che-Cheng Chang, Jr-Jung Lin, Chih-Han Lin
  • Fin field effect transistor (FinFET) device and method for forming the same
    Patent number: 10686077
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Yung-Jung Chang
  • Structure and formation method of semiconductor device structure
    Patent number: 10686060
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Wei-Ting Chen, Yu-Cheng Liu
  • Structure of semiconductor device structure having fins
    Patent number: 10686059
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Yu-Cheng Liu, Wei-Ting Chen
  • Enlarging spacer thickness by forming a dielectric layer over a recessed interlayer dielectric
    Patent number: 10679989
    Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Han Lin, Che-Cheng Chang, Horng-Huei Tseng
  • Fin field effect transistor
    Patent number: 10672908
    Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Mechanisms for forming FINFET device
    Patent number: 10672796
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung-Jung Chang
  • Semiconductor device and method
    Patent number: 10665700
    Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Che-Cheng Chang, Po-Chi Wu