Abstract: An interconnect structure is provided. The interconnect structure includes a transistor on a substrate, a first dielectric layer over the transistor, a first metal line through the first dielectric layer, a second dielectric layer over the first dielectric layer, and a via through the second dielectric layer and on the first metal line. A first side surface of the first dielectric layer includes a first portion in direct contact with the first metal line and a second portion in direct contact with the via, and the first portion of the first side surface of the first dielectric layer is aligned with the second portion of the first side surface of the first dielectric layer.

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.

Abstract: A device comprises a first metal structure, a dielectric structure, a dielectric residue, and a second metal structure. The dielectric structure is over the first metal structure. The dielectric structure has a stepped sidewall structure. The stepped sidewall structure comprises a lower sidewall and an upper sidewall laterally set back from the lower sidewall. The dielectric residue is embedded in a recessed region in the lower sidewall of the stepped sidewall structure of the dielectric structure. The second metal structure extends through the dielectric structure to the first metal structure.

Abstract: A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.

Abstract: A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: A mobile communication device is provided with a processor. The processor is configured to receive a request for starting a Mobile Originated (MO) service, determine a plurality of remaining usage quotas for the MO service, which correspond to a plurality of subscriber numbers, and select one of the subscriber numbers for starting the MO service according to the remaining usage quotas.

Abstract: A method for displaying SIM card slot information for use in a device including M SIM card slots, each of which may have a SIM card inserted therein or no SIM card inserted therein. The method includes the following steps. A set of predetermined rules are first determined by the device. Statuses of the M SIM card slots corresponding to the set of predetermined rules are then acquired. Information regarding N of the M SIM card slots are displayed on a display unit of the device according to the set of predetermined rules determined by the current associated network and the acquired statuses of the M SIM card slots, where N<M and N>=1.

Abstract: A mobile communication device is provided with a processor. The processor is configured to receive a request for starting a Mobile Originated (MO) service, determine a plurality of remaining usage quotas for the MO service, which correspond to a plurality of subscriber numbers, and select one of the subscriber numbers for starting the MO service according to the remaining usage quotas.

Abstract: A method for displaying SIM card slot information for use in a device including M SIM card slots, each of which may have a SIM card inserted therein or no SIM card inserted therein. The method includes the following steps. A set of predetermined rules are first determined by the device. Statuses of the M SIM card slots corresponding to the set of predetermined rules are then acquired. Information regarding N of the M SIM card slots are displayed on a display unit of the device according to the set of predetermined rules determined by the current associated network and the acquired statuses of the M SIM card slots, where N<M and N>=1.

Abstract: A method for calculating leakage current associated with an integrated circuit, includes selecting a sampling point at which an input signal for the integrated circuit is in a quiescent state and determining the leakage current associated with the integrated circuit using the selected sampling point.

Abstract: A water dispersible granule includes the ingredients of wetting agent, dispersing agent, binder, disintegratant, acid, base, carrier and pesticide, wherein the above ingredients are combined to be 100%. All the above components of insecticide are mixed with water and extruded. The extruded material is baked in an oven that has operation temperature set from 40° C. to 50° C. and the baked material ground into small granules by machine or manpower.

Abstract: A heat dissipation assembly comprises a printed circuit board (PCB) (20), a chip (30) and a heat sink (10). The PCB comprises a grounding circuit and four through apertures (22) in the grounding circuit. The chip is mounted on the PCB, and is surrounded by the through apertures. The heat sink has four metal columns (16) depending from a bottom surface of a base (12) thereof, the columns corresponding to the four through apertures. A method of assembling the heat dissipation assembly includes the steps of: mounting a chip on a PCB; inserting metal columns of a heat sink into corresponding through apertures of the PCB; and welding the metal columns in the through apertures so that the heat sink is in intimate thermal contact with an upper surface of the chip.

Abstract: A heat dissipation assembly comprises a printed circuit board (PCB) (20), a chip (30) and a heat sink (10). The PCB comprises a grounding circuit and four through apertures (22) in the grounding circuit. The chip is mounted on the PCB, and is surrounded by the through apertures. The heat sink has four metal columns (16) depending from a bottom surface of a base (12) thereof, the columns corresponding to the four through apertures. A method of assembling the heat dissipation assembly includes the steps of: mounting a chip on a PCB; inserting metal columns of a heat sink into corresponding through apertures of the PCB; and welding the metal columns in the through apertures so that the heat sink is in intimate thermal contact with an upper surface of the chip.

Abstract: A process is provided for generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for a system having a plurality of repetitive subcircuits. The process includes the steps of: receiving an input layout database including a plurality of geometric objects including cells representing the IC design, each of the cells including a plurality of polygons; identifying a plurality of repetitive cells of the input layout database, the repetitive cells being associated with the repetitive sub-circuits; recognizing at least one pattern of the repetitive cells; defining at least one cut region of the input layout database, the cut region being defined by physical layout coordinates, the cut region intersecting a corresponding pattern of the repetitive cells; and generating a synoptic layout database.