Patents by Inventor Che-Chi Lee
Che-Chi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11915777Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: February 10, 2022Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Che-Chi Lee, Terrence B. McDaniel, Kehao Zhang, Albert P. Chan, Clement Jacob, Luca Fumagalli, Vinay Nair
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Publication number: 20230178586Abstract: Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: January 27, 2023Publication date: June 8, 2023Applicant: Micron Technology, Inc.Inventor: Che-Chi Lee
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Patent number: 11616119Abstract: Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: April 21, 2021Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventor: Che-Chi Lee
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Publication number: 20220358971Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: February 10, 2022Publication date: November 10, 2022Applicant: Micron Technology, Inc.Inventors: Che-Chi Lee, Terrence B. McDaniel, Kehao Zhang, Albert P. Chan, Clement Jacob, Luca Fumagalli, Vinay Nair
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Publication number: 20220344450Abstract: Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: April 21, 2021Publication date: October 27, 2022Applicant: Micron Technology, Inc.Inventor: Che-Chi Lee
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Patent number: 11282548Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: May 4, 2021Date of Patent: March 22, 2022Assignee: Micron Technology, Inc.Inventors: Che-Chi Lee, Terrence B. McDaniel, Kehao Zhang, Albert P. Chan, Clement Jacob, Luca Fumagalli, Vinay Nair
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Patent number: 10825691Abstract: Methods, apparatuses, and systems related to stack a semiconductor structure are described. An example method includes stacking a semiconductor structure between electrode materials having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a third silicate material on the second nitride. The method further includes forming a third nitride on the third silicate material. The method further includes using a wet etch process to increase a width between electrode materials. The method further includes using a dry etch process to remove a portion of materials within the semiconductor structure.Type: GrantFiled: August 29, 2019Date of Patent: November 3, 2020Assignee: Micron Technology, Inc.Inventor: Che-Chi Lee
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Patent number: 10347487Abstract: Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: November 14, 2017Date of Patent: July 9, 2019Assignee: Micron Technology, Inc.Inventors: Che-Chi Lee, Hiromitsu Oshima
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Publication number: 20190148136Abstract: Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: November 14, 2017Publication date: May 16, 2019Inventors: Che-Chi Lee, Hiromitsu Oshima
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Publication number: 20160043089Abstract: Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes forming a mask on a number of capacitor elements in an array, such that a space between vertically and horizontally adjacent capacitor elements is fully covered and a space between diagonally adjacent capacitor elements is partially covered and forming a support lattice in a support material by etching the support material to remove portions of the support material below the openings in the mask.Type: ApplicationFiled: October 7, 2015Publication date: February 11, 2016Inventors: Zhimin Song, Che-Chi Lee, Brett Busch
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Patent number: 9184167Abstract: Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes forming a mask on a number of capacitor elements in an array, such that a space between vertically and horizontally adjacent capacitor elements is fully covered and a space between diagonally adjacent capacitor elements is partially covered and forming a support lattice in a support material by etching the support material to remove portions of the support material below the openings in the mask.Type: GrantFiled: August 21, 2012Date of Patent: November 10, 2015Assignee: Micron Technology, Inc.Inventors: Zhimin Song, Che-Chi Lee, Brett Busch
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Patent number: 9076757Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials.Type: GrantFiled: August 12, 2013Date of Patent: July 7, 2015Assignee: Micron Technology, Inc.Inventor: Che-Chi Lee
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Patent number: 8921977Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.Type: GrantFiled: December 21, 2011Date of Patent: December 30, 2014Assignee: Nan Ya Technology CorporationInventors: Jen Jui Huang, Che Chi Lee, Shih Shu Tsai, Cheng Shun Chen, Shao Ta Hsu, Chao Wen Lay, Chun I Hsieh, Ching Kai Lin
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Publication number: 20140054745Abstract: Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes forming a mask on a number of capacitor elements in an array, such that a space between vertically and horizontally adjacent capacitor elements is fully covered and a space between diagonally adjacent capacitor elements is partially covered and forming a support lattice in a support material by etching the support material to remove portions of the support material below the openings in the mask.Type: ApplicationFiled: August 21, 2012Publication date: February 27, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Zhimin Song, Che-Chi Lee, Brett Busch
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Publication number: 20130323902Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials.Type: ApplicationFiled: August 12, 2013Publication date: December 5, 2013Applicant: Micron Technology, Inc.Inventor: Che-Chi Lee
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Patent number: 8518788Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials.Type: GrantFiled: August 11, 2010Date of Patent: August 27, 2013Assignee: Micron Technology, Inc.Inventor: Che-Chi Lee
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Publication number: 20130161786Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: Nan Ya Technology CorporationInventors: Jen Jui Huang, Che Chi Lee, Shih Shu Tsai, Cheng Shun Chen, Shao Ta Hsu, Chao Wen Lay, Chun I. Hsieh, Ching Kai Lin
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Publication number: 20120040507Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials.Type: ApplicationFiled: August 11, 2010Publication date: February 16, 2012Inventor: Che-Chi Lee